Micron Technology Incorporated

Cypress Semiconductor Corporation

Honeywell International Inc.

William L Larson

Shaoping Li

Theodore Zhu

Harry Liu

Yong Lu

Anthony Arrott

Lonny L Berg

Joel A Drewes

Romney R Katti

Cheisan J Yue

Eric E Vogt

Mohammed A Fathimulla

A passivated magneto-resistive bit structure is disclosed in which surfaces subjects to oxidation or corrosion are protected. In one embodiment, a bit structure is encapsulated by means of an etch stop barrier material. In another embodiment an etch stop barrier material protects the top of a bit structure and dielectric spacers protect the side walls.

Passivated magneto-resistive bit structure and passivation method therefor

A varactor has a plurality of alternating P&#x2212; wells and N+ regions formed in a silicon layer. Each of the P&#x2212; wells forms a first N+/P&#x2212; junction with the N+ region on one of its side and a second N+/P&#x2212; junction with the N+ region on the other of its sides. A gate oxide is provided over each of the P&#x2212; wells, and a gate silicon is provided over each of the gate oxides. The potential across the gate silicons and the N+ regions controls the capacitance of the varactor.

Varactor with improved tuning range

A magnetic bit structure for a magneto-resistive memory is disclosed that has bit ends that are sufficiently large to accommodate a minimum size contact or via hole. By providing such an arrangement, the magnetic bit structure may be fabricated using conventional contact and/or via processing steps. As such, the cost of manufacturing the device may be reduced, and the overall achievable yield may be increased.

Method for manufacture of magneto-resistive bit structure

MRAM architectures are disclosed that produce an increased write margin and write selectivity without significantly reducing the packing density of the memory. The major axes of the magneto-resistive bits are offset relative to the axes of the digital lines to produce a magnetic field component from the digital line current that extends along the major axis of the magneto-resistive bits.

Methods of increasing write selectivity in an MRAM

A device and method of manufacture for a low capacitance overvoltage protection device. This is accomplished through the use of PiN diodes to shunt overvoltage away from internal circuit elements. PiN diodes are useful because they exhibit a low capacitance in reverse bias mode. Radio frequency integrated circuits and other integrated circuits operated at high frequency are sensitive to capacitance. This invention protects against circuit damage due to overvoltage events while keeping capacitance low through the use of PiN diodes.

Overvoltage protection device using pin diodes

Passivated magneto-resistive bit structure

Magneto-resistive bit structure and method of manufacture therefor

MRAM architectures for increased write selectivity

MRAM architecture using offset bits for increased write selectivity

A passivated magneto-resistive bit structure is disclosed in which surfaces subject to oxidation or corrosion are protected. In one embodiment a bit structure is encapsulated by means of an etch stop barrier material. In another embodiment an etch stop barrier material protects the top of a bit structure and dielectric spacers protect the side walls.

Growing community of inventors

Eden Prairie, MN, United States of America

William L Larson