International Business Machines Corporation

Advanced Micro Devices Corporation

Motorola Corporation

William Kurt Lewchuk

Ravi Kumar Arimilli

John Michael Kaiser

Michael Scott Allen

William Alexander Hughes

Gerald David Zuraski, Jr

Scott A White

Alexander J Branover

Frederick Daniel Weber

Derrick R Meyer

Michael T Clark

Jonathan Mercer Owen

Guhan Krishnan

Hebbalalu S Ramagopal

Carl D Dietz

Douglas Richard Beard

A system and method for data allocation in a shared cache memory of a computing system are contemplated. Each cache way of a shared set-associative cache is accessible to multiple sources, such as one or more processor cores, a graphics processing unit (GPU), an input/output (I/O) device, or multiple different software threads. A shared cache controller enables or disables access separately to each of the cache ways based upon the corresponding source of a received memory request. One or more configuration and status registers (CSRs) store encoded values used to alter accessibility to each of the shared cache ways. The control of the accessibility of the shared cache ways via altering stored values in the CSRs may be used to create a pseudo-RAM structure within the shared cache and to progressively reduce the size of the shared cache during a power-down sequence while the shared cache continues operation.

Method for way allocation and way locking in a cache

A processor has pre-cache and post-cache buffers. The pre-cache (or LS1) buffer stores memory operations which have not yet probed the data cache. The post-cache (or LS2) buffer stores the memory operations which have probed the data cache. As a memory operation probes the data cache, it is moved from the LS1 buffer to the LS2 buffer. Since misses and stores which have probed the data cache do not reside in the LS1 buffer, the scan logic for selecting memory operations from the LS1 buffer to probe the data cache may be simple and low latency, allowing for the load latency to the data cache for load hits to be relatively low. Furthermore, since the memory operations which have probed the data cache have been removed from the LS1 buffer, the simple scan logic may support high performance features such as allowing hits to proceed under misses, etc. Additionally, since the LS2 buffer receives memory operations which have probed the data cache and thus may be waiting for retirement or fill data from memory, reprobing from the LS2 buffer may be less performance critical than probing from the LS1 buffer. Accordingly, the LS2 buffer may be made deeper than the LS1 buffer to queue numerous misses and/or stores. In this fashion, it may be possible to maximize the use of external bus bandwidth to service the misses.

Load/store unit having pre-cache and post-cache queues for low latency load memory operations

A processor is presented including a cache unit coupled to a bus interface unit (BIU). Address signal selection and masking functions are performed by circuitry within the BIU rather than within the cache unit, and physical addresses produced by the BIU are stored within the TLB. As a result, address signal selection and masking circuitry (e.g., a multiplexer and gating logic) are eliminated from a critical speed path within the cache unit, allowing the operational speed of the cache unit to be increased. The cache unit stores data items, and produces a data item corresponding to a received linear address. A translation lookaside buffer (TLB) within the cache unit stores multiple linear addresses and corresponding physical addresses. When a physical address corresponding to the received linear address is not found within the TLB, the cache unit passes the linear address to the BIU. The BIU includes address translation circuitry, a multiplexer, and gating logic, and returns the physical address corresponding to the linear address to the cache unit. The cache unit stores the physical address and the linear address within the TLB. The processor may also include a programmable control register and a microexecution unit. Upon detecting a change in state of an external masking signal, the microexecution unit may flush the contents of the TLB and modify a masking bit within the control register to reflect a new state of the masking signal.

Computer system including a novel address translation mechanism

A system and method for using a toggle command for setting and releasing a lock, i.e. a locktoggle. In an exemplary computer system, one or more processors are each coupled to a bus bridge through separate high speed connections, such as a pair of uni-directional address buses with respective source-synchronous clock lines and a bi-directional data bus with attendant source-synchronous clock lines. The locktoggle command is used to transmit both a lock request and an unlock request from a processor to a system coherency. point, e.g. the bus bridge. The system coherency point acknowledges when the lock has been established or released. While the lock is active, other processors are inhibited. from accessing at least the memory locations for which the lock was initiated. Locks are thus established at the system coherency point, which may advantageously allow for locking functionality in a non-shared bus system. The use of the locktoggle command may advantageously allow for the use of a single command code point, leaving other points available for other uses.

Minimizing use of bus command code points to request the start and end of a lock

A processor employs an SMC check apparatus. The SMC check apparatus may minimize the number of explicit SMC checks performed for non-cacheable stores. Cacheable stores may be handled using any suitable mechanism. For non-cacheable stores, the processor tracks whether or not the in-flight instructions are cached. Upon encountering a non-cacheable store, the processor inhibits an SMC check if the in-flight instructions are cached. Since, for performance reasons, the code stream is often cached, non-cacheable stores may frequently be able to skip an explicit, complex, and time consuming SMC check. Performance of non-cacheable stores (and memory throughput overall) may be increased. The handling of non-cacheable stores as described herein may be particularly beneficial to video data manipulations, which may frequently be of a non-cacheable memory type and which may be important to the overall performance of a computer system.

Minimizing self-modifying code checks for uncacheable memory types

A system and method are provided that use a determination of bad data parity and the state of an error signal (Derr.sub.--) as a functional signal indicating a specific type of error in a particular system component. If the Derr.sub.-- signal is active, the parity error recognized by the CPU was caused by a correctable condition in a data providing device. In this instance, the processor will read the corrected data from a buffer without reissuing a fetch request. When the CPU finds a parity error, but Derr.sub.-- is not active a more serious fault condition is identified (bus error or uncorrectable multibit error) requiring a machine level interrupt, or the like. And, when no parity is found by the CPU and Derr.sub.-- is not active, then the data is known to be valid and the parity/ECC latency is eliminated, thereby saving processing cycle time.

Low latency error reporting for high performance bus

A method and system are provided for communicating between devices. A signal is output from a first device. In response to the signal, at least one action is initiated by a second device. An indication is output of whether the second device completed the action and of whether operation of the second device is independent of the first device reoutputting the signal.

System and method for communicating between devices

An efficient multiprocessor address transfer mechanism is utilized within a data processing system including a plurality of bus devices. The present invention places control of the flow of address bus operations within the system controller rather than the bus devices, e.g., a master processor. The system controller issues an address bus grant, in response to an address bus request from a particular bus device, and shortly after that issues another signal notifying the granted bus device that it must now disable the address bus. Furthermore, upon receipt of the signal indicating disablement of the address bus, other bus devices may then snoop, or sample, the address bus.

System and method for allocating bus resources in a data processing

A system and method which utilizes a unique bus protocol in conjunctions plural Dval.sub.-- control signals to minimize the dead time between blocks of data being transferred between components is a data processing system. The present invention introduces another latch-to-latch data valid control signal and alternates the usage of this signal during back to back data transfers from the same or different bus devices. In this manner the restore and tristate dead cycles are totally overlapped with the data transfer and the minimum possible number of dead cycle(s) is achieved between different blocks of data transfers. With the method of the present invention, data providers alternately activate the Dval.sub.-- signals and data receivers look at all Dval.sub.-- signals and if any one of them is active, then the data is considered valid and can be read.

Alternating data valid control signals for high performance data transfer

A multiprocessor system utilizing a plurality of bus devices coupled via a shared bus utilizes a specially coded signal to notify a bus device initiating a read or a read with intent to modify operation that the requested data, or cache line, is in a modified state within a cache of another bus device. Unlike the modified response signal, this special signal is sent along with the requested data from the one bus device to the requesting bus device, indicating that this data has priority over any data being sent from the memory system coupled to the shared bus. The present invention allows for cache-to-cache and cache-to-memory-and-cache operations.

Cache coherency in a multiprocessing system

A multiprocessing system utilizes a bus protocol having two response windows. The first response window is at a fixed latency from the transmission of a bus request and/or address, while the second response window, utilized for coherency reporting, is placed a configurable number of clock cycles after the bus request and address to allow for longer access, or snoop, times to perform a cache directory look-up within other bus devices. The first response window reports error or flow control and error status. Furthermore, a method had been described, which implements the reporting of response information in a flexible and high performance manner.

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Austin, TX, United States of America

William Kurt Lewchuk