Sun Microsystems, Inc.

William K Lam

Mohamed Soufi

Victor A Chang

David S Allison

Thomas M McWilliams

Zhaoyun Xing

Shrenik M Mehta

Nasser Nouri

Deepankar Bairagi

Harihara Ganesan

Yick Kei Wong

Techniques are disclosed for automatically determining whether a potential constraint set to be applied to a portion of a circuit are overconstrained. An environment circuit supplies inputs to the circuit portion. Embodiments of the invention recognize that if the environment circuit produces a set of outputs that contain a pattern that is not present in the potential constraint set, then the potential constraint set is overconstrained. A verification tool establishes the properties for the environmental circuit based on the potential constraint set. If the verification tool determines that the outputs produced by the environment circuit conflict with the properties of the environment circuit, then the verification tool concludes that the potential constraint set is overconstrained, because the environment circuit produces a pattern that is not present in the potential constraint set. Advantageously, the laborious and error-prone process of manually determining the proper inputs to apply during formal verification is avoided.

Eliminate false passing of circuit verification through automatic detecting of over-constraining in formal verification

A design of an integrated circuit is first verified using directed and/or random test cases. For a cover directive not covered by the directed and/or random test cases, a property is created, where a simulation trace that causes the property to fail covers the cover directive. Thereafter, the property is evaluated, and dependent on the evaluation, the simulation trace is dumped and stored for subsequent exercising of the cover directive.

Technique for generating input stimulus to cover properties not covered in random simulation

A method for providing verification for a simulation design, including obtaining the simulation design comprising a programming language interface system call, encoding a target of the programming language interface system call into the simulation design to obtain a first modified simulation design, modifying the programming language interface system call to reference the target in the first modified simulation design to obtain a second modified simulation design, and verifying the second modified simulation design using a simulation testbench.

PLI-less co-simulation of ISS-based verification systems in hardware simulators

A method for providing verification for a first simulation image involves removing nodes from the first simulation image to produce an optimized image and an optimized nodes image, simulating the optimized image, invoking the optimized nodes image if debugging is selected, reconstructing a second simulation image using the optimized image and the optimized nodes image, simulating the second simulation image to gather simulation data, and debugging the first simulation image using simulation data.

Method for simulation with optimized kernels and debugging with unoptimized kernels

A method for transforming a behavioral specification involves converting the behavioral specification into a diagram representation, converting a delay from the diagram representation if the behavioral specification comprises a delay, generating a compliant cycle diagram from the diagram representation, and deriving a cycle equivalent behavioral specification from the compliant cycle diagram.

Method for transforming behavioral architectural and verification specifications into cycle-based compliant specifications

A system for tracing a simulation design involves an encoded assertion asserting a value of a node of the simulation design at a point in a simulation, a fanin cone detection facility configured to obtain a fanin cone for the encoded assertion, a waveform trace facility configured to obtain waveform data including a history of signal values for the node, and a simulation toolkit configured to obtain node data using the fanin cone and the waveform data.

Method and apparatus for generating minimal node data and dynamic assertions for a simulation

A method for providing verification for a simulation design involves analyzing a simulation design using a testbench comprising a rapid bug detection tool, and if a bug is detected, adding a bug isolation tool to the testbench, and isolating and eliminating the bug using the testbench comprising the bug isolation tool.

Method and apparatus for detection and isolation during large scale circuit verification

The invention provides a method for detecting and isolating software bugs and generating a minimal set of stimuli to reproduce the bugs. The present invention utilizes a recursive algorithm to compare the output of successively smaller software blocks of a program in development to a verified output sample. The smallest software blocks which are found to contain a bug are isolated. For each of these isolated blocks, the smallest input vector is determined such that the application of this vector to the block expresses the bug. The present invention utilizes a separate recursive algorithm to determine these minimal vectors.

Method and apparatus for automatically isolating minimal distinguishing stimuli in design verification and software development

A system and method for processing a variable looping statement into a constant looping statement to enable loop unrolling. A lower bound and an upper bound of the loop index within the variable looping statement are determined. A constant looping statement is then formed using the lower bound and upper bound to define a range over which the loop index varies within the constant looping statement. The constant looping statement further includes a conditional statement that reflects conditions in the initial expression and/or the exit expression of the variable looping statement. The conditional statement controls execution of the body of the generated constant looping statement, which includes the body from the original variable looping statement. Loop unrolling may then be performed on the generated constant looping statement.

Method of transforming variable loops into constant loops

A method for dynamically customizing object code for simulation includes obtaining a statically generated object (SGO) and a first test vector, segmenting the SGO with a marker node to generate a segmented SGO comprising a plurality of SGO segments, generating a first simulation profile using the segmented SGO and the first test vector, locating a first unexercised segment of the plurality of SGO segments using the first simulation profile, and generating a first reduced SGO by removing the first unexercised segment from the segmented SGO.

Boosting simulation performance by dynamically customizing segmented object codes based on stimulus coverage

One embodiment of the present invention provides a system that facilitates generating a simulation module for testing a system design. The system operates by receiving a system specification, which specifies correct behavior for modules within the system design. The system also receives modules that are individually designed to this system specification. The system then compares the modules with the system specification to identify nonfunctioning modules that can include either missing modules or incorrect modules. The system also determines an interface for the nonfunctioning modules from the system specification, which specifies input and output requirements for these nonfunctioning modules. The system then generates the simulation module. This simulation module can function in place of the nonfunctioning module and can simulate a functionality assigned to the nonfunctioning module.

Method and apparatus to facilitate generating simulation modules for testing system designs

One embodiment of the present invention provides a system that facilitates representing a shape within a layout of an integrated circuit using a Boolean expression. The system operates by first receiving a representation of the shape and then converting the representation of the shape into a Boolean expression that is formed using a Boolean coordinate system expressed in a two-dimensional Gray code. The system then performs operations on the shape by performing Boolean operations on the Boolean expression for the shape.

Using Boolean expressions to represent shapes within a layout of an integrated circuit

The invention is a method and apparatus for generating one or more Steiner trees representing a connection of at least two points. In accordance with an embodiment of the method, a Boolean network function is generated which represents a network of interconnects connecting the at least two points. A binary decision diagram (BDD) for the Boolean network function is generated, the BDD having a root and at least one variable node. The number of vertices for at least one variable node of the BDD is determined. The solution values for one or more of the variables of the Boolean network function are determined in accordance with a path(s) through the BDD from the root to one or more of the variable nodes. In one embodiment, the Boolean network function represents interconnects in an encoded space containing the points to be connected, the interconnects having no greater than &ldquo;n&rdquo; segments and arranged to join at a joint. In accordance with this embodiment, the solution values yielded by the BDD path(s) comprise the coordinates of the interconnect joint.

Method and apparatus for generating n-segment steiner trees

The invention is a method and apparatus for optimizing a real function in the Boolean domain. In accordance with an embodiment of the method, the real function is represented as a Boolean function. A binary decision diagram for the Boolean function is generated, the binary decision diagram having a root and at least one variable node. The number of vertices for at least one variable node of the binary decision diagram is determined. The function is optimized by selecting a path or paths from the root to at least one variable node of the binary decision diagram having the least number of vertices. The solution values of one or more variables of the Boolean function are determined in accordance with the path(s) through the binary decision diagram. These values comprise an optimized solution set for the real function.

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Newark, CA, United States of America

William K Lam