International Business Machines Corporation

Globalfoundries Inc.

William K Henson

Dureseti Chidambarrao

Michael Patrick Chudzik

Kern Rim

Chandrasekharan Kothandaraman

Brian Joseph Greene

Unoh Kwon

Shreesh Narasimha

Bruce Bennett Doris

Vijay Narayanan

Renee Tong Mo

Huiming Bu

Clement Hsingjen Wann

Jeffrey W Sleight

Dechao Guo

Siddarth A Krishnan

Edward J Nowak

Shu-Jen Han

Judson Robert Holt

Wesley Charles Natzle

Devendra K Sadana

Takashi Ando

Huilong Zhu

Jack Allan Mandelman

Ghavam G Shahidi

Stephen W Bedell

Chun-chen Yeh

Keith Kwong Hon Wong

Ying Di Zhang

Zhijiong Luo

Christian Lavoie

Martin Michael Frank

Richard Stephan Wise

Yue Liang

Deok-Kee Kim

Ricardo Alves Donaton

Yaocheng Liu

Xiaojun Yu

Naim Moumen

Hongwen Yan

Yanfeng Wang

Hung Y Ng

Rohit Pal

Xinlin Wang

Edward P Maciejewski

Myung-Hee Na

Richard Stephen Wise

William C Wille

Michael D Steigerwalt

Mukesh Vijay Khare

Kuldeep Amarnath

Johan W Weijtmans

Wei He

Ravikumar Ramachandran

Kathryn Turner Schonenberg

Gregory Gower Freeman

Byeongju Park

Philip A Fisher

Ming Cai

Sameer Hemchand Jain

Rashmi Jha

Maryjane Brodsky

Charlotte DeWan Adams

Liyang Song

Amanda L Tessier

Paul Chung-Muh Chang

Ying Zhang

Michael P Chudzik

Bruce B Doris

A device including a p-type semiconductor device and an n-type semiconductor device on a semiconductor substrate. The n-type semiconductor device includes a gate structure having a high-k gate dielectric. A carbon dopant in a concentration ranging from 1&#xd7;10atoms/cmto 1&#xd7;10atoms/cmis present at an interface between the high-k gate dielectric of the gate structure for the n-type semiconductor device and the semiconductor substrate. Methods of forming the aforementioned device are also disclosed.

Work function adjustment by carbon implant in semiconductor devices including gate structure

A complementary metal oxide semiconductor (CMOS) device including a substrate including a first active region and a second active region, wherein each of the first active region and second active region of the substrate are separated by from one another by an isolation region. A n-type semiconductor device is present on the first active region of the substrate, in which the n-type semiconductor device includes a first portion of a gate structure. A p-type semiconductor device is present on the second active region of the substrate, in which the p-type semiconductor device includes a second portion of the gate structure. A connecting gate portion provides electrical connectivity between the first portion of the gate structure and the second portion of the gate structure. Electrical contact to the connecting gate portion is over the isolation region, and is not over the first active region and/or the second active region.

Complementary metal oxide semiconductor (CMOS) device having gate structures connected by a metal gate conductor

A structure includes a substrate; a transistor disposed over the substrate, the transistor comprising a fin comprised of Silicon that is implanted with Carbon; and a gate dielectric layer and gate metal layer overlying a portion of the fin that defines a channel of the transistor. In the structure a concentration of Carbon within the fin is selected to establish a desired voltage threshold of the transistor. Methods to fabricate a FinFET transistor are also disclosed. Also disclosed is a planar transistor having a Carbon-implanted well where the concentration of the Carbon within the well is selected to establish a desired voltage threshold of the transistor.

Threshold voltage adjustment for thin body MOSFETs

A semiconductor structure including a p-channel field effect transistor (pFET) device located on a surface of a silicon germanium (SiGe) channel is provided in which the junction profile of the source/drain region is abrupt. The abrupt source/drain junctions for pFET devices are provided by forming an N- or C-doped Si layer directly beneath a SiGe channel layer which is located above a Si substrate. A structure is provided in which the N- or C-doped Si layer (sandwiched between the SiGe channel layer and the Si substrate) has approximately the same diffusion rate for a p-type dopant as the overlying SiGe channel layer. Since the N- or C-doped Si layer and the overlying SiGe channel layer have substantially the same diffusivity for a p-type dopant and because the N- or C-doped Si layer retards diffusion of the p-type dopant into the underlying Si substrate, abrupt source/drain junctions can be formed.

Method and structure for pFET junction profile with SiGe channel

A method is provided that includes forming a high-k dielectric etch stop layer over at least a first conductivity type semiconductor device on a first portion of a substrate and at least a second conductivity type semiconductor device on a second portion of the semiconductor device. A first stress-inducing layer is deposited over the first conductivity type semiconductor device and the second conductivity type semiconductor device. The portion of the first stress-inducing layer that is formed over the second conductivity type semiconductor device is then removed with an etch that is selective to the high-k dielectric etch stop layer to provide an exposed surface of second portion of the substrates that includes at least the second conductivity type semiconductor device. A second stress-inducing layer is then formed over the second conductivity type semiconductor device.

Structure and method for using high-K material as an etch stop layer in dual stress layer process

Adjustment of a switching threshold of a field effect transistor including a gate structure including a Hi-K gate dielectric and a metal gate is achieved and switching thresholds coordinated between NFETs and PFETs by providing fixed charge materials in a thin interfacial layer adjacent to the conduction channel of the transistor that is provided for adhesion of the Hi-K material, preferably hafnium oxide or HfSiON, depending on design, to semiconductor material rather than diffusing fixed charge material into the Hi-K material after it has been applied. The greater proximity of the fixed charge material to the conduction channel of the transistor increases the effectiveness of fixed charge material to adjust the threshold due to the work function of the metal gate, particularly where the same metal or alloy is used for both NFETs and PFETs in an integrated circuit; preventing the thresholds from being properly coordinated.

Method and structure for work function engineering in transistors including a high dielectric constant gate insulator and metal gate (HKMG)

Structure and method for using high-k material as an etch stop layer in dual stress layer process

A semiconductor structure including a p-channel field effect transistor (pFET) device located on a surface of a silicon germanium (SiGe) channel is provided in which the junction profile of the source region and the drain region is abrupt. The abrupt source/drain junctions for pFET devices are provided in this disclosure by forming an N- or C-doped Si layer directly beneath a SiGe channel layer which is located above a Si substrate. A structure is thus provided in which the N- or C-doped Si layer (sandwiched between the SiGe channel layer and the Si substrate) has approximately the same diffusion rate for a p-type dopant as the overlying SiGe channel layer. Since the N- or C-doped Si layer and the overlying SiGe channel layer have substantially the same diffusivity for a p-type dopant and because the N- or C-doped Si layer retards diffusion of the p-type dopant into the underlying Si substrate, abrupt source/drain junctions can be formed.

A low energy surface is formed by a high temperature anneal of the surfaces of trenches on each side of a gate stack. The material of the semiconductor layer reflows during the high temperature anneal such that the low energy surface is a crystallographic surface that is at a non-orthogonal angle with the surface normal of the semiconductor layer. A lattice mismatched semiconductor material is selectively grown on the semiconductor layer to fill the trenches, thereby forming embedded lattice mismatched semiconductor material portions in source and drain regions of a transistor. The embedded lattice mismatched semiconductor material portions can be in-situ doped without increasing punch-through. Alternately, a combination of intrinsic selective epitaxy and ion implantation can be employed to form deep source and drain regions.

Self-aligned embedded SiGe structure and method of manufacturing the same

Methods for fabricating gate electrode/high-k dielectric gate structures having an improved resistance to the growth of silicon dioxide (oxide) at the dielectric/silicon-based substrate interface. In an embodiment, a method of forming a transistor gate structure comprises: incorporating nitrogen into a silicon-based substrate proximate a surface of the substrate; depositing a high-k gate dielectric across the silicon-based substrate; and depositing a gate electrode across the high-k dielectric to form the gate structure. In one embodiment, the gate electrode comprises titanium nitride rich in titanium for inhibiting diffusion of oxygen.

High-k dielectric gate structures resistant to oxide growth at the dielectric/silicon substrate interface and methods of manufacture thereof

A method of forming a semiconductor device is provided that includes forming a Ge-containing layer atop a p-type device regions of the substrate. Thereafter, a first dielectric layer is formed in a second portion of a substrate, and a second dielectric layer is formed overlying the first dielectric layer in the second portion of the substrate and overlying a first portion of the substrate. Gate structures may then formed atop the p-type device regions and n-type device regions of the substrate, in which the gate structures to the n-type device regions include a rare earth metal.

High-K metal gate CMOS

Multiple types of gate stacks are formed on a doped semiconductor well. A high dielectric constant (high-k) gate dielectric is formed on the doped semiconductor well. A metal gate layer is formed in one device area, while the high-k gate dielectric is exposed in other device areas. Threshold voltage adjustment oxide layers having different thicknesses are formed in the other device areas. A conductive gate material layer is then formed over the threshold voltage adjustment oxide layers. One type of field effect transistors includes a gate dielectric including a high-k gate dielectric portion. Other types of field effect transistors include a gate dielectric including a high-k gate dielectric portion and a first threshold voltage adjustment oxide portions having different thicknesses. Field effect transistors having different threshold voltages are provided by employing different gate dielectric stacks and doped semiconductor wells having the same dopant concentration.

Method of providing threshold voltage adjustment through gate dielectric stack modification

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Beacon, NY, United States of America

William K Henson