International Business Machines Corporation

Taiwan Semiconductor Manufacturing Comp. Ltd.

Massachusetts Institute of Technology

William Joseph Gallagher

Eugene John O'Sullivan

Naigang Wang

Lubomyr Taras Romankiw

Hariklia Deligianni

Shy-Jay Lin

Devendra K Sadana

Effendi Leobandung

Robert Fontana

Bucknell Chapman Webb

Philipp Herget

David William Abraham

Philip Louis Trouilloud

Mingyuan Song

Chien-Min Lee

Jonathan Zanhong Sun

Mark B Ketchen

Christopher Peter D'Emic

Yu Lu

John Casimir Slonczewski

Can Bayram

Andrew John Kellock

Maurice Mason

Joonah Yoon

Ghavam G Shahidi

Daniel Christopher Worledge

John Francis Bulzacchelli

Chwen Yu

Stuart Stephen Parkin

John De Brosse

Chung H Lam

Roy E Scheuerlein

Yu-Der Chih

Anthony J Annunziata

Solomon Assefa

Hiroki Noguchi

Michael C Gaidis

Luc Thomas

Yu Luo

Thomas K Worthington

Gaurav Gupta

Stuart P Parkin

Philip Edward Batson

Sathana Kitayaporn

Harry-Hak-Lay Chuang

Zhiqiang Wu

Yi-Chun Shih

John Kenneth DeBrosse

Stuart Stephen Papworth Parkin

Tien-Wei Chiang

Chao-Kun Hu

Robert L Sandstrom

Chun-Jung Lin

Robert B Laibowitz

Ko-Tao Lee

James Harvey Kaufman

Mark A Jaso

Tomas Apostol Palacios

Yen-Lin Huang

Dale J Pearson

Daniel Piedra

Timothy Rea Dinger

Marinus Johannes Petrus Hopstaken

Alan W Kleinsasser

Ming Yuan Song

Arthur Davidson

Edward August Giess

Yi-Chieh Chiu

Stanley Irwin Raider

Chien-Ye Lee

Aranava Gupta

Walter Eidelloth

Jenn-Jou Wu

A magnetic memory device includes a magnetic tunnel junction (MTJ) stack, a spin-orbit torque (SOT) induction wiring disposed over the MTJ stack, a first terminal coupled to a first end of the SOT induction wiring, a second terminal coupled to a second end of the SOT induction wiring, and a shared selector layer coupled to the first terminal.

SOT-MRAM with shared selector

A micro-electromechanical device and method of manufacture are disclosed. A sacrificial layer is formed on a silicon substrate. A metal layer is formed on a top surface of the sacrificial layer. Soft magnetic material is electrolessly deposited on the metal layer to manufacture the micro-electromechanical device. The sacrificial layer is removed to produce a metal beam separated from the silicon substrate by a space.

Micro-electromechanical device having a soft magnetic material electrolessly deposited on a palladium layer coated metal beam

A device includes a substrate having a first side and a second side, a first transistor that includes a first gate over a first protrusion and a first source region and a first drain region interposing the first protrusion, a first buried contact disposed adjacent to the first protrusion and having at least a portion extending into the substrate, a first contact plug disposed over the first drain region, first conductive lines disposed over the first contact plug and electrically connecting to the first drain region by the first contact plug, first via penetrating through the substrate and connecting the first buried contact; and second conductive lines disposed over the second side of the substrate and electrically connecting to the first via. The first buried contact is electrically connecting to the first source region or the first gate.

Semiconductor device and method for forming the same

Various embodiments of the present disclosure are directed towards a memory device including a shunting layer overlying a spin orbit torque (SOT) layer. A magnetic tunnel junction (MTJ) structure overlies a semiconductor substrate. The MTJ structure includes a free layer, a reference layer, and a tunnel barrier layer disposed between the free and reference layers. A bottom electrode via (BEVA) underlies the MTJ structure, where the BEVA is laterally offset from the MTJ structure by a lateral distance. The SOT layer is disposed vertically between the BEVA and the MTJ structure, where the SOT layer continuously extends along the lateral distance. The shunting layer extends across an upper surface of the SOT layer and extends across at least a portion of the lateral distance.

MRAM device having self-aligned shunting layer

A magnetic memory device includes a magnetic tunnel junction (MTJ) stack, a spin-orbit torque (SOT) induction wiring disposed over the MTJ stack, a first terminal coupled to a first end of the SOT induction wiring, a second terminal coupled to a second end of the SOT induction wiring, and a selector layer coupled to the first terminal.

Magnetic device and magnetic random access memory

Some examples relate to a method for forming a semiconductor device. The method comprises forming a pattern definition stack over a substrate, the pattern definition stack comprising a transfer layer, an interlayer arranged over the transfer layer, and a patterning layer arranged over the interlayer. The method further comprises forming a first opening in the patterning layer to expose an upper surface of the interlayer and etching the interlayer with an at least partially isotropic etchant through the first opening to form a recessed cavity. The method further comprises forming a conformal layer over the interlayer and the patterning layer to fill the first opening, and etching the conformal layer and the transfer layer with an anisotropic etch to form a second opening in the transfer layer. The method also comprises depositing a hard mask material in the second opening.

Method for forming MTJS with lithography-variation independent critical dimension

Micro-electromechanical device having a soft magnetic material electrolessly deposited on a metal layer

Present disclosure relates to magnetic materials, chips having magnetic materials, and methods of forming magnetic materials. In certain embodiments, magnetic materials may include a seed layer, and a cobalt-based alloy formed on seed layer. The seed layer may include copper, cobalt, nickel, platinum, palladium, ruthenium, iron, nickel alloy, cobalt-iron-boron alloy, nickel-iron alloy, and any combination of these materials. In certain embodiments, the chip may include one or more on-chip magnetic structures. Each on-chip magnetic structure may include a seed layer, and a cobalt-based alloy formed on seed layer. In certain embodiments, method may include: placing a seed layer in an aqueous electroless plating bath to form a cobalt-based alloy on seed layer. In certain embodiments, the aqueous electroless plating bath may include sodium tetraborate, an alkali metal tartrate, ammonium sulfate, cobalt sulfate, ferric ammonium sulfate and sodium borohydride and has a pH between about 9 to about 13.

Electrolessly formed high resistivity magnetic materials

An on-chip magnetic structure includes a palladium activated seed layer and a substantially amorphous magnetic material disposed onto the palladium activated seed layer. The substantially amorphous magnetic material includes nickel in a range from about 50 to about 80 atomic % (at. %) based on the total number of atoms of the magnetic material, iron in a range from about 10 to about 50 at. % based on the total number of atoms of the magnetic material, and phosphorous in a range from about 0.1 to about 30 at. % based on the total number of atoms of the magnetic material. The magnetic material can include boron in a range from about 0.1 to about 5 at. % based on the total number of atoms of the magnetic material.

High resistivity iron-based, thermally stable magnetic material for on-chip integrated inductors

In some embodiments, the present application provides a magnetic memory device. The magnetic memory device comprises a bottom electrode, and a first synthetic anti-ferromagnetic (SyAF) layer including a first pinning layer and a second pinning layer disposed over the bottom electrode and having opposite magnetization directions and separated by a first spacer layer. The magnetic memory device further comprises a reference layer disposed over the first pair of pinning layers and a free layer disposed over the reference layer and separated from the reference layer by a tunneling barrier layer. The magnetic memory device further comprises a second synthetic anti-ferromagnetic (SyAF) layer including a third pinning layer and a fourth pinning layer disposed over the free layer and having opposite magnetization directions and separated by a second spacer layer.

Magnetic memory device with balancing synthetic anti-ferromagnetic layer

In a method of manufacturing a semiconductor device, a magnetic random access memory (MRAM) cell structure is formed. The MRAM cell structure includes a bottom electrode, a magnetic tunnel junction (MTJ) stack and a top electrode. A first insulating cover layer is formed over the MRAM cell structure. A second insulating cover layer is formed over the first insulating cover layer. An interlayer dielectric (ILD) layer is formed. A contact opening in the ILD layer is formed, thereby exposing the second insulating cover layer. A part of the second insulating cover layer and a part of the first insulating cover layer are removed, thereby exposing the top electrode. A conductive layer is formed in the opening contacting the top electrode. The second insulating cover layer has an oxygen getter property.

Magnetic random access memory and manufacturing method thereof

In some embodiments, the present application provides a memory device. The memory device includes a ferromagnetic free layer; a non-magnetic barrier layer overlying the ferromagnetic free layer; and a superparamagnetic free layer overlying the non-magnetic barrier layer.

Memory device with superparamagnetic layer

An on-chip magnetic structure includes a magnetic material comprising cobalt in a range from about 80 to about 90 atomic % (at. %) based on the total number of atoms of the magnetic material, tungsten in a range from about 4 to about 9 at. % based on the total number of atoms of the magnetic material, phosphorous in a range from about 7 to about 15 at. % based on the total number of atoms of the magnetic material, and palladium substantially dispersed throughout the magnetic material.

High resistivity soft magnetic material for miniaturized power converter

Growing community of inventors

Ardsley, NY, United States of America

William Joseph Gallagher