Motorola Corporation

Freescale Semiconductor,inc.

William J Ooms

Jerald A Hallmark

Daniel S Marshall

Jamal Ramdani

Ravindranath Droopad

Jonathan K Abrokwah

Jenn-Hwa Huang

Jun J Wang

Kurt W Eisenbeiser

Carl Lynn Shurboff

Jeffrey M Finder

Yang Wang

Herbert Goronkin

Chowdary Ramesh Koripella

Robert Michael Gardner

X Theodore Zhu

Corey D Overgaard

Jay A Curless

David Wilcox

Saied N Tehrani

Mark A Durlam

James S Irwin

Zhiyi Jimmy Yu

Clifford D Leitch

Joseph W Bostaph

Stephen P Rogers

Robert J Higgins, Jr

Marino J Martinez

Dominic Francis Gervasio

Charles W Shanley

Lyndee L Hilt

Rene M Delgado

Ellen Lan

Christopher K Dyer

Ernie Schirmann

Richard E Barnett

Michael G Taylor

Zhiyi Yi

Method and apparatus utilizing monocrystalline insulator

A fuel processor and integrated fuel cell including a monolithic three-dimensional multilayer ceramic carrier structure defining a fuel reformer and including an integrated fuel cell stack. The reformer includes a vaporization zone, a reaction zone including a catalyst, and an integrated heater. The integrated heater is thermally coupled to the reaction zone. The fuel processor further includes an inlet channel for liquid fuel and an outlet channel for hydrogen enriched gas. The fuel processor is formed utilizing multi-layer ceramic technology in which thin ceramic layers are assembled then sintered to provide miniature dimensions in which the encapsulated catalyst converts or reforms inlet fuel into a hydrogen enriched gas.

Fuel processor with integrated fuel cell utilizing ceramic technology

High quality epitaxial layers of monocrystalline materials can be grown overlying large silicon wafers by first growing an accommodating buffer layer ( ) on a silicon wafer ( ). The accommodating buffer layer ( ) is a layer of monocrystalline material spaced apart from the silicon wafer ( ) by an amorphous interface layer ( ) of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline accommodating buffer layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. Utilizing this technique permits the fabrication of thin film pyroelectric devices ( ) on a monocrystalline silicon substrate.

Pyroelectric device on a monocrystalline semiconductor substrate and process for fabricating same

High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. One way to achieve the formation of a compliant substrate includes first growing an accommodating buffer layer ( ) on a silicon wafer ( ). The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer ( ) of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy, epitaxial growth of single crystal silicon onto single crystal oxide, and epitaxial growth of Zintl phase materials. Quantum well infrared photodetectors ( ) can be grown on the high quality epitaxial monocrystalline material formed on such compliant substrates to create highly reliable devices having reduced costs.

Quantum well infrared photodetector and method for fabricating same

High quality epitaxial layers of piezoelectric material materials can be grown overlying large silicon wafers by first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer.

Acoustic wave device and process for forming the same

High quality epitaxial layers of oxide can be grown overlying large silicon wafers by first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous intermediate layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous intermediate layer. Waveguides may be formed of high quality monocrystalline material atop the monocrystalline buffer layer. The waveguides can suitably be formed to modulate the wave. Monolithic integration of oxide based electro-optic devices with III-V based photonics and Si circuitry is fully realized.

Electro-optic structure and process for fabricating same

A method of fabricating a field effect transistor including doping a continuous blanket layer in a semiconductor substrate structure adjacent the surface to include a source area and a drain area spaced from the source area. A high dielectric constant insulator layer is positioned on the surface of the semiconductor substrate structure overlying the continuous blanket layer to define a gate area between the source and drain areas. A gate contact on the insulator layer is selected to provide a work function difference that depletes the doped layer beneath the insulator layer. Further, the doped layer depth and dosage are designed such that the doped layer is depleted beneath the insulator layer by the selected work function difference of the gate contact and the semiconductor substrate.

Method and apparatus for creating a voltage threshold in a FET

A hybrid integrated circuit is provided that has a monocrystalline substrate such as silicon and a compound semiconductor layer such as gallium arsenide or indium phosphide. An optical communications port may be formed on the hybrid integrated circuit. Electrical equipment may be provided that includes electrical components. At least a given one of the components may be a hybrid integrated circuit. Data used for the operation of one of the given integrated circuit may be provided to the given integrated circuit through the optical communications port on that integrated circuit. The data may be loaded rapidly in real time due to the wide bandwidth of the optical communications port.

Reconfigurable systems using hybrid integrated circuits with optical ports

A fuel cell system and method of forming the fuel cell system including a base portion, formed of a singular body, and having a major surface. At least one fuel cell membrane electrode assembly is formed on the major surface of the base portion. A fluid supply channel including a mixing chamber is defined in the base portion and communicating with the fuel cell membrane electrode assembly for supplying a fuel-bearing fluid to the membrane electrode assembly. An exhaust channel including a water recovery and recirculation system is defined in the base portion and communicating with the membrane electrode assembly. The membrane electrode assembly and the cooperating fluid supply channel and cooperating exhaust channel forming a single fuel cell assembly.

Direct methanol fuel cell system and method of fabrication

A thermoelectric power generator and method of generating thermoelectric power in a steam power cycle utilizing latent steam heat including a condenser, a heat source, such as steam, and at least one thermoelectric module. The condenser includes a plurality of condenser tubes each having included therein a heat extractor. The heat source is in communication with the condenser and is characterized as providing thermal energy to the condenser. The at least one thermoelectric module, including a plurality of thermoelectric elements, is positioned in communication with at least one of the plurality of condenser tubes so that thermal energy flows through the thermoelectric elements thereby generating electrical power.

Thermoelectric power generator and method of generating thermoelectric power in a steam power cycle utilizing latent steam heat

A field effect transistor with an enhanced dielectric constant gate insulator including spaced apart source and drain terminals positioned on a substrate structure so as to define a gate area therebetween. A layer of laterally strained, enhanced dielectric constant dielectric material is epitaxially grown on the substrate structure in the gate area, and a gate metal is positioned on the layer of dielectric material to form a gate terminal in the gate area.

Enhanced dielectric constant gate insulator

A semiconductor structure comprises a silicon substrate (,), one or more layers of single crystal oxides (,), and an interface (,) between the silicon substrate and the one or more layers of single crystal oxides, the interface manufactured with a crystalline material which matches the lattice constant of silicon. The interface is an atomic layer of silicon, oxygen, and a metal in the form XSiO,, where X is a metal.

Semiconductor structure having a crystalline alkaline earth metal oxide interface with silicon

A method for fabricating a semiconductor structure comprises the steps of providing a silicon substrate (,) having a surface (,); forming on the surface of the silicon substrate an interface (,) comprising a single atomic layer of silicon, oxygen, and a metal; and forming one or more layers of a single crystal oxide (,) on the interface. The interface comprises an atomic layer of silicon, oxygen, and a metal in the form XSiO,, where X is a metal.

Method for fabricating a semiconductor structure having a crystalline alkaline earth metal oxide interface with silicon

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Chandler, AZ, United States of America

William J Ooms