Motorola Corporation

Freescale Semiconductor,inc.

Other

Applied Materials, Inc.

Motorola Mobility LLC

William J Dauksher

Wei E Wu

Byung-Sung Kwak

Douglas J Resnick

Pawitter Jit Mangat

David P Mancini

Donald F Weston

Jeffrey H Baker

Kevin J Nordquist

Albert Alec Talin

Robert W Baird

Young Sir Chung

Arnold W Yanof

Steven R Young

Doug J Resnick

Ngoc V Le

Andy E Hooper

Philip Armin Seese

Byung Sung Kwak

Kurt W Eisenbeiser

Emmett Howard

Nety M Krishna

Bernard J Roman

Jon J Candelaria

Danny L Thompson

C Joseph Mogab

Bradley M Melnick

Cesar M Garza

Pawitter J S Mangat

Pawitter Jit Singh Mangat

Kathy A Gehoski

Roy Allen Huston

Pawitterjit S Mangat

Jon Candelaria

In accordance with a specific embodiment, a method of processing a semiconductor substrate is disclosed whereby the substrate is thinned, and the dice formed on the substrate are singulated by a common process. Trench regions are formed on a backside of the substrate. An isotropic etch of the backside results in a thinning of the substrate while maintaining the depth of the trenches, thereby facilitating singulation of the die.

Ultra-thin die and method of fabricating same

Concepts and methods are provided to reduce the cost and complexity of thin film battery (TFB) high volume manufacturing by eliminating and/or minimizing the use of conventional physical (shadow) masks. Laser scribing and other alternative physical maskless patterning techniques meet certain or all of the patterning requirements. In one embodiment, a method of manufacturing thin film batteries comprises providing a substrate, depositing layers corresponding to a thin film battery structure on the substrate, the layers including, in order of deposition, a cathode, an electrolyte and an anode, wherein at least one of the deposited layers is unpatterned by a physical mask during deposition, depositing a protective coating, and scribing the layers and the protective coating. Further, the edges of the layers may be covered by an encapsulation layer. Furthermore, the layers may be deposited on two substrates and then laminated to form the thin film battery.

Method for high volume manufacturing of thin film batteries

This invention relates to semiconductor devices, microelectronic devices, micro electro mechanical devices, microfluidic devices, photonic devices, and more particularly to a lithographic template, a method of forming the lithographic template and a method for forming devices with the lithographic template. The lithographic template () is formed having a substrate (), a transparent conductive layer () formed on a surface () of the substrate () by low pressure sputtering to a thickness that allows for preferably 90% transmission of ultraviolet light therethrough, and a patterning layer () formed on a surface () of the transparent conductive layer (). The template () is used in the fabrication of a semiconductor device () for affecting a pattern in device () by positioning the template () in close proximity to semiconductor device () having a radiation sensitive material formed thereon and applying a pressure to cause the radiation sensitive material to flow into the relief image present on the template. Radiation is then applied through the template so as to cure portions of the radiation sensitive material and define the pattern in the radiation sensitive material. The template () is then removed to complete fabrication of semiconductor device ().

Lithographic template and method of formation and use

A lithographic template, a method of forming the lithographic template and a method for forming devices with the lithographic template is provided. The lithographic template () and the method of making comprises forming a transparent conductive layer () over a substrate (). A SiCN layer () is formed over the transparent conductive layer (), and a patterning layer () formed on the SiCN layer (). The SiCN layer () is converted to an SiOlayer by applying an Oplasma (). The SiOlayer prevents damage to the transparent conductive layer () during cleaning and provides a binding mechanism for the imprint release coating.

A process for forming a catalyst layer for carbon nanotube growth comprising forming a catalyst layer having a first and second portion over one of a cathode metal layer or a ballast resistor layer; patterning a photoresist over the first portion; etching the second portion with a chlorine/argon plasma; removing the photoresist with an ash process; and removing the veils and preparing the surface for carbon nanotube growth with a semi-aqueous hydroxylamine solution.

Plasma etch process for defining catalyst pads on nanoemissive displays

A direct imprinting process for Step and Flash Imprint Lithography includes providing () a substrate (); forming () an etch barrier layer () on the substrate; patterning () the etch barrier layer with a template () while curing with ultraviolet light through the template, resulting in a patterned etch barrier layer and a residual layer () on the substrate; and performing () an etch to substantially remove the residual layer. Optionally, a patterning layer () may be formed on the substrate () prior to forming the etch barrier layer (). Additionally, an adhesive layer () may be applied () between the substrate () and the etch barrier layer ().

Direct imprinting of etch barriers using step and flash imprint lithography

A process is provided for fabricating a viabetween bonded wafers without undercutting an organic bonding material. The process for forming the viain a structure including a dielectric materialand an organic bonding material, comprises forming a resist materialon the dielectric layerand etching through the dielectric layerand the organic bonding materialwith 60CF/20Ar/60CHF/20N. The resist may then be removed with an anisotropic high density oxygen plasma.

Plasma etch process for multilayer vias having an organic layer with vertical sidewalls

This invention relates to semiconductor devices, microelectronic devices, micro electro mechanical devices, microfluidic devices, and more particularly to an improved lithographic template including a repaired defect, a method of fabricating the improved lithographic template, a method for repairing defects present in the template, and a method for making semiconductor devices with the improved lithographic template. The lithographic template () is formed having a relief structure () and a repaired gap defect () within the relief structure (). The template () is used in the fabrication of a semiconductor device () for affecting a pattern in device () by positioning the template () in close proximity to semiconductor device () having a radiation sensitive material formed thereon and applying a pressure to cause the radiation sensitive material to flow into the relief structure present on the template. Radiation is then applied through the template so as to further cure portions of the radiation sensitive material and further define the pattern in the radiation sensitive material. The template () is then removed to complete fabrication of semiconductor device ().

Lithographic template having a repaired gap defect method of repair and use

A semiconductor device is formed by patterning a resist layer using a rim phase shifting mask. A multilayer or single patterning layer to form the different phase-shifting regions and opaque regions is used to manufacture the rim phase shifting mask. First phase shifting regions are formed by transferring an opening in the multilayer or single patterning layer through an opaque layer and a transparent substrate. At least portions of the same multilayer or single patterning layer are used to recess the opaque layer a predetermined distance to form rims (second phase shifting regions). The first phase-shifting regions phase shift the light traveling through them 180 degrees relative to the light traveling through the rims, thereby increasing the contrast of the light traveling through the rim phase shifting mask.

Method of forming a rim phase shifting mask and using the rim phase shifting mask to form a semiconductor device

The lithographic template is formed having a substrate, an optional etch stop layer formed on a surface of the substrate, and a patterning layer formed on a surface of the etch stop layer. The template is used in the fabrication of a semiconductor device for affecting a pattern in the device by positioning the template in close proximity to the semiconductor device having a radiation sensitive material formed thereon and applying a pressure to cause the radiation sensitive material to flow into the relief image present on the template. Radiation is then applied through the template so as to further cure portions of the radiation sensitive material and further define the pattern in the radiation sensitive material. The template is then removed to complete fabrication of the semiconductor device.

This invention relates to semiconductor devices, microelectronic devices, micro electro mechanical devices, microfluidic devices, and more particularly to a lithographic template, a method of forming the lithographic template and a method for forming devices with the lithographic template. The lithographic template ( ) is formed having a substrate ( ), an optional etch stop layer ( ) formed on a surface ( ) of the substrate ( ), and a patterning layer ( ) formed on a surface ( ) of the etch stop layer ( ). The template ( ) is used in the fabrication of a semiconductor device ( ) for affecting a pattern in device ( ) by positioning the template ( ) in close proximity to semiconductor device ( ) having a radiation sensitive material formed thereon and applying a pressure to cause the radiation sensitive material to flow into the relief image present on the template. Radiation is then applied through the template so as to further cure portions of the radiation sensitive material and further define the pattern in the radiation sensitive material. The template ( ) is then removed to complete fabrication of semiconductor device ( ).

A method of forming a hard mask for use in the formation of a refractory radiation mask including providing a membrane structure, forming a radiation absorbing layer to be patterned on the membrane structure, forming a hard mask layer on the surface of the membrane structure, the hard mask layer including a material system having a nominally zero stress and therefore reduced distortion of the membrane structure, and patterning the hard mask layer.

Low stress hard mask formation method during refractory radiation mask fabrication

A method for fabricating a patterning mask is disclosed in which a membrane layer is deposited on a first surface of a substrate. Patterned and unpatterned portions of the substrate are then defined on a second surface of the substrate. A majority of the thickness of substrate in the unpatterned portions is then dry etched to partially define a strut having sidewalls that are substantially perpendicular to the first surface. Wet etching is then performed to etch through the remaining thickness of the substrate to expose the bottom surface of the membrane layer and completely define the strut. Scattering elements may then be formed over the membrane layer. In one embodiment, the substrate is silicon and has a ( ) orientation and an edge of the silicon struts is aligned to a &lcub; &rcub; plane. In another embodiment, an edge of the silicon struts is aligned to a &lcub; &rcub; plane.

Growing community of inventors

Mesa, AZ, United States of America

William J Dauksher