International Business Machines Corporation

Kabushiki Kaisha Toshiba

Advanced Micro Devices Corporation

Other

William J Cote

Daniel C Edelstein

Oliver Desmond Patterson

Anthony K Stamper

Tak H Ning

Kerry Bernstein

Wilbur David Pricer

John Anthony Bracchitta

Xiaomeng Chen

Arthur C Winslow

Yi Feng

Michael F Lofaro

Michael A Leach

John Edward Cronin

Theodorus E Standaert

Robert Dennis Miller

Alfred Grill

Sampath Purushothaman

Timothy Joseph Dalton

Elbert Emin Huang

Hiroyuki Yano

Griselda Bonilla

Terry Allen Spooner

Muthumanickam Sankarapandian

Donald Francis Canaperi

Willi Volksen

Naftali Eliahu Lustig

John Christopher Arnold

Eric Jeffrey White

Mahadevaiyer Krishnan

James Gardner Ryan

Katsuya Okumura

Carter W Kaanta

Satya Venkata Nitta

Geraud J Dubois

E Todd Ryan

Terrance M Wright

Pei-ing P Lee

Karey L Holland

Effendi Leobandung

Son Van Nguyen

Stephen McConnell Gates

Ravikumar Ramachandran

Laertis Economikos

Babar Ali Khan

John Anthony Fitzsimmons

Min Yang

Dae-Gyu Park

Johnathan E Faltermeier

Thomas L McDevitt

Xinhui Wang

Donald M Kenney

Kenneth Jay Stein

Scott David Halle

Max Gerald Levy

Nancy Anne Greco

Arpan Pravin Mahorowala

Yunsheng Song

Young-Hee Kim

James M Rice

Joyce C Liu

Felix Patrick Anderson

Paul M Feeney

William C Wille

Gill Yong Lee

Donna Rizzone Cote

Kenneth M Davis

Markus M Kirchhoff

James Anthony Tornello

Scott Alan Estes

Michael T Brigham

Thomas H Ivers

Peter E Biolsi

Michael A Cobb

Philip Murphy

Edward Jack Gordon

Michael Joseph MacDonald

Michael L Kerbaugh

William R Hill

Allan Ward Upham

Prakash Chimanlal Dev

James Hannah

Thomas Edwin Sandwick

Bernd M Vollmer

Mark E Lagus

Manfred Hauf

Dean Allen Schaffer

Cheryl A Hoffman

Jeffrey A Robinson

James K Paulsen

John Fritche

Robert C Bausmith

Robert W Sweetser

Michael P Guse

Steven Moskowitz

George James Slusser

Stuart H Wolff

Victor Vynorius

Ys Suh

Allan Ibm United Kingdom Limited Upham

Test structures and method for detecting defects using the same. A probe-able voltage contrast (VC) comb test structure that includes first, second and third probe pads, a comb-like structure including grounded tines, floating tines between the grounded tines, switching devices coupled with an end portion of each floating tine, and connecting the floating tines to the second probe pad, and the third probe pad being a control pad which controls the switching devices. A probe-able VC serpentine test structure that includes first, second, third and fourth probe pads, a comb-like structure including grounded tines, floating tines between the grounded tines and each floating tine connected together between the second and third probe pads, switching devices connected to an end portion of each floating tine and connecting the floating tines to the second and third probe pads, and the fourth probe pad being a control pad which controls the switching devices.

Probe-able voltage contrast test structures

A method including providing fins etched from a semiconductor substrate and covered by an oxide layer and a nitride layer, the oxide layer being located between the fins and the nitride layer, removing a portion of the fins to form an opening, forming a dielectric spacer on a sidewall of the opening, and filling the opening with a fill material, wherein a top surface of the fill material is substantially flush with a top surface of the nitride layer. The method may further include forming a deep trench capacitor in-line with one of the fins, removing the nitride layer to form a gap between the fins and the fill material, wherein the fill material has re-entrant geometry extending over the gap, and removing the re-entrant geometry and causing the gap between the fins and the fill material to widen.

Uniform finFET gate height

Methods of fabricating replacement metal gate transistors using bi-layer a hardmask are disclosed. By utilizing a bi-layer hardmask comprised of a first layer of nitride, followed by a second layer of oxide, the topography issues caused by transition regions of gates are mitigated, which simplifies downstream processing steps and improves yield.

Replacement metal gate transistors using bi-layer hardmask

Methods of minimizing or eliminating plasma damage to low k and ultra low k organosilicate intermetal dielectric layers are provided. The reduction of the plasma damage is effected by interrupting the etch and strip process flow at a suitable point to add an inventive treatment which protects the intermetal dielectric layer from plasma damage during the plasma strip process. Reduction or elimination of a plasma damaged region in this manner also enables reduction of the line bias between a line pattern in a photoresist and a metal line formed therefrom, and changes in the line width of the line trench due to a wet clean after the reactive ion etch employed for formation of the line trench and a via cavity. The reduced line bias has a beneficial effect on electrical yields of a metal interconnect structure.

Methods to mitigate plasma damage in organosilicate dielectrics

Monitoring a process sector in a production facility includes establishing a tool defect index associated with a process sector in the production facility. The tool defect index includes a signal representing a defect factor associated with a tool in the process sector. Monitoring the process also requires determining whether the defect factor is a known defect factor or an unknown defect factor, and analyzing a unit from the tool if the defect factor is an unknown defect factor. Monitoring the process further requires identifying at least one defect on the unit from the tool, establishing that the at least one defect is a significant defect, determining cause of the significant defect, and creating an alert indicating that the tool associated with the process sector is producing units having significant defects.

Monitoring a process sector in a production facility

Structures with improved solder bump connections and methods of fabricating such structures are provided herein. The structure includes a trench formed in a dielectric layer which has at least a portion thereof devoid of a fluorine boundary layer. The structure further includes a copper wire in the trench having at least a bottom portion thereof in contact with the non-fluoride boundary layer of the trench. A lead free solder bump is in electrical contact with the copper wire.

Structures and methods for improving solder bump connections in semiconductor devices

Method for reducing resist poisoning. The method includes the steps of forming a first structure in a dielectric on a substrate, reducing amine related contaminants from the dielectric and the substrate prior to a formation of a second structure on the substrate such that the amine related contaminates will not diffuse out from either the substrate or the dielectric, wherein the reducing utilizes a plasma treatment which one of chemically ties up the amine related contaminates and binds, traps, or consumes the amine related contaminates during subsequent processing steps, forming the second structure on the substrate, and after the forming of the first structure, preventing poisoning of a resist layer in subsequent processing by the reducing.

Method for reducing amine based contaminants

A method for reducing resist poisoning is provided. The method includes forming a first structure in a dielectric on a substrate and reducing amine related contaminants from the dielectric and the substrate created after the formation of the first structure. The method further includes forming a second structure in the dielectric. A first organic film may be formed on the substrate which is then heated and removed from the substrate to reduce the contaminant. Alternatively, a plasma treatment or cap may be provided. A second organic film is formed on the substrate and patterned to define a second structure in the dielectric.

Semiconductor structure having reduced amine-based contaminants

Structures and a method are disclosed for grounding gate-stack and/or silicon active region front-end-of-line structures on a silicon-on-insulator (SOI) substrate, which may be used as test structures for VC inspection. In one embodiment, a structure includes a grounded bulk silicon substrate having the SOI substrate thereover, the SOI substrate including a silicon-on-insulator (SOI) layer and a buried oxide (BOX) layer; the silicon active region having at least one finger element within the SOI layer, the at least one finger element isolated by a shallow trench isolation (STI) layer; and a polysilicon ground intersecting the at least one finger element and extending through the STI layer and the BOX layer to the grounded bulk silicon substrate, the polysilicon ground contacting the silicon active region and the grounded bulk silicon substrate.

Grounding front-end-of-line structures on a SOI substrate

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Poughquag, NY, United States of America

William J Cote