International Business Machines Corporation

William H-l Ma

Mark Charles Hakey

Steven J Holmes

Toshiharu Furukawa

David V Horak

William R Tonti

James Marc Leas

Paul A Rabidoux

Donald Walter Rakowski

Patricia McGuiness Marmillion

Ramachandra Divakauni

Jack Allan Mandelman

Wayne Michael Delia

William A Ma

Jack A Mandclman

A method of manufacturing provides a vertical transistor particularly suitable for high density integration and which includes potentially independent gate structures on opposite sides of a semiconductor pillar formed by etching or epitaxial growth in a trench. The gate structure is surrounded by insulating material which is selectively etchable to isolation material surrounding the transistor. A contact is made to the lower end of the pillar (e.g. the transistor drain) by selectively etching the isolation material selective to the insulating material. The upper end of the pillar is covered by a cap and sidewalls of selectively etchable materials so that gate and source connection openings can also be made by selective etching with good registration tolerance. A dimension of the pillar in a direction parallel to the chip surface is defined by a distance between isolation regions and selective etching and height of the pillar is defined by thickness of a sacrificial layer.

Vertical dual gate field effect transistor

Disclosed is a method that forms a conductive layer on a substrate and patterns sacrificial structures above the conductive layer. Next, the invention forms sidewall spacers adjacent the sacrificial structures using a spacer material capable of undergoing dimensional change, after which the invention removes the sacrificial structures in processing that leaves the sidewall spacers in place. The invention then protects selected ones of the sidewall spacers using a sacrificial mask and leaves the other ones of the sidewall spacers unprotected. This allows the invention to selectively expose the unprotected sidewall spacers to processing that changes the size of the unprotected sidewall spacers. This causes the unprotected sidewall spacers have a different size than protected sidewall spacers. Then, the invention removes the sacrificial mask and patterns the conductive layer using the sidewall spacers as a gate conductor mask to create differently sized gate conductors on the substrate. Following this, the invention removes the sidewall spacers and forms the source, drain, and channel regions adjacent the gate conductors.

Method of independent P and N gate length control of FET device made by sidewall image transfer technique

Methods are provided that use disposable and permanent films to dope underlying layers through diffusion. Additionally, methods are provided that use disposable films during implantation doping and that provide a surface from which to dope underlying materials. Some of these disposable films can be created from a traditionally non-disposable film and made disposable. In this manner, solvents may be used that do not etch underlying layers of silicon-based materials. Preferably, deep implantation is performed to form source/drain regions, then an anneal step is performed to activate the dopants. A conformal layer is deposited and implanted with dopants. One or more anneal steps are performed to create very shallow extensions in the source/drain regions.

Methods using disposable and permanent films for diffusion and implantation doping

An etching process using germanium hard mask () includes forming a dielectric layer () over a major surface () of a semiconductor substrate () and depositing a metallic germanium layer () over the dielectric layer (). The metallic germanium layer () is patterned through a photo resist () to form the germanium hard mask (). The dielectric layer () is selectively etched through the germanium hard mask () to form a dielectric hard mask (), through which the semiconductor substrate () is subsequently etched. After forming the dielectric hard mask (), the germanium hard mask () is stripped away by oxidizing the metallic germanium hard mask () to transform it into a layer () of germanium oxide and rinsing the semiconductor substrate () in water to remove the germanium oxide layer (). Preferably, the germanium hard mask () is removed before etching the semiconductor substrate ().

Method for etching a semiconductor substrate using germanium hard mask

A vertical transistor particularly suitable for high density integration includes potentially independent gate structures on opposite sides of a semiconductor pillar formed by etching or epitaxial growth in a trench. The gate structure is surrounded by insulating material which is selectively etchable to isolation material surrounding the transistor. A contact is made to the lower end of the pillar (e.g. the transistor drain) by selectively etching the isolation material selective to the insulating material. The upper end of the pillar is covered by a cap and sidewalls of selectively etchable materials so that gate and source connection openings can also be made by selective etching with good registration tolerance. A dimension of the pillar in a direction parallel to the chip surface is defined by a distance between isolation regions and selective etching and height of the pillar is defined by thickness of a sacrificial layer.

A computer display system which displays an image and a magnified portion of the image. The magnified portion of the image is selected un,der control of a pointing device connected to the computer. A method is described for changing the characteristics of the magnified portion. A configuration utility which creates the magnified portion of the display includes a menu of display properties for the magnified portion. The properties are selected from the display menu, and each refresh of the area within the magnified portion of the image is refreshed with the selected properties. In a text/browser application, the background color, text color, text style and size may be selected differently than the remaining portion of the image displayed on the computer display.

Method for selecting display parameters of a magnifiable cursor

A composite, layered, integrated circuit formed by bonding of insulator layers on wafers provides for combination of otherwise incompatible technologies such as trench capacitor DRAM arrays and high performance, low power, low voltage silicon on insulator (SOI) switching transistors and short signal propagation paths between devices formed on respective wafer layers of a chip. In preferred embodiments, an SOI wafer is formed by hydrophilic bonding of a wafer over an integrated circuit device and then cleaving a layer of the second wafer away using implanted hydrogen and low temperature heat treatment. Further wafers of various structures and compositions may be bonded thereover and connections between circuit elements and connection pads in respective wafers made using short vias that provide fast signal propagation as well as providing more numerous connections than can be provided on chip edges.

SIO stacked DRAM logic

SOI stacked DRAM logic

Method using disposable and permanent films for diffusion and implant doping

Features of two or more distinct sizes designed to optimize performance of an integrated circuit device are formed by transferring a pattern from a resist patterned with features of a single minimum feature size for which a resist exposure tool is optimized to a layer of preferably soluble material such as germanium oxide. Portions of this pattern are then enlarged using a block-out mask and the resulting pattern transferred to a further underlying layer preferably using an anisotropic reactive ion etch. The soluble material can then be removed leaving a robust mask with differing feature sizes for further processing. Preferably, Damascene conductive lines and vias are formed by providing an insulator as the further underlying material and filling the openings with metal or other conductive material.

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Fishkill, NY, United States of America

William H-l Ma