Qualcomm Incorporated

International Business Machines Corporation

William Goodall, Iii

Anthony Correale, Jr

Benjamin Bowers

Jeffrey Herbert Fischer

Fadi Adel Hamdan

Tracey Della Rova

Animesh Datta

Ohsang Kwon

Satyanarayana Sahu

Joshua Lance Puckett

Philip Michael Iles

Wolfgang Friedrich Bultmann

Aspects disclosed in the detailed description include integrated circuit (IC) design methods using engineering change order (ECO) cell architectures. In particular, exemplary aspects provide a fill algorithm that is both single- and multi-row aware, considers a poly-pitch count, and utilizes metallization of the 'empty space' relative to a suite of available fill cells. The algorithm is also aware of timing critical logic elements and may place ECO fill cells in near proximity to such timing sensitive circuits or other margin critical circuits to allow for decoupling or, if there is a logic error, an ECO cell is placed such that the ECO cell is well positioned to be repurposed as a delay circuit or other function to aid in margin control. For maximum flexibility, the algorithm may also address both pre- and post-route applications.

Integrated circuit (IC) design methods using engineering change order (ECO) cell architectures

Disclosed systems and methods pertain to finfet based integrated circuits designed with logic cell architectures which support multiple diffusion regions for n-type and p-type diffusions. Different diffusion regions of each logic cell can have different widths or fin counts. Abutting two logic cells is enabled based on like fin counts for corresponding p-diffusion regions and n-diffusion regions of the two logic cells. Diffusion fills are used at common edges between the two logic cells for extending lengths of diffusion, based on the like fin counts. The logic cell architectures support via redundancy and the ability to selectively control threshold voltages of different logic cells with implant tailoring. Half-row height cells can be interleaved with standard full-row height cells.

Standard cell architecture for diffusion based on fin count

Complementary metal oxide semiconductor (MOS) (CMOS) standard cell circuits employing metal lines in a first metal layer used for routing, and related methods are disclosed. In one aspect, a CMOS standard cell circuit includes first supply rail, second supply rail, and metal lines disposed in the first metal layer. One or more of the metal lines are dynamically cut corresponding to a first cell boundary and a second cell boundary of the CMOS standard cell such that the metal lines have cut edges corresponding to the first and second cell boundaries. Metal lines not cut corresponding to the first and second cell boundaries can be used to interconnect nodes of the CMOS standard cell circuit. Dynamically cutting the metal lines allows the first metal layer to be used for routing, reducing routing in other metal layers such that fewer vias and metal lines are disposed above the first metal layer.

Complementary metal oxide semiconductor (CMOS) standard cell circuits employing metal lines in a first metal layer used for routing, and related methods

At least one configurable circuit cell with a continuous active region includes at least one center subcell, a first-side subcell, and a second-side subcell. Each center subcell includes first and second pMOS transistors and first and second nMOS transistors. The first pMOS transistor has a first-pMOS-transistor gate, source, and drain. The first-pMOS-transistor source is coupled to a first voltage source. The second pMOS transistor has a second-pMOS-transistor gate, source, and drain. The second-pMOS-transistor source is coupled to the first voltage source. The first-pMOS-transistor drain and the second-pMOS-transistor drain are a same drain. The first nMOS transistor has a first-nMOS-transistor gate, source, and drain. The first-nMOS-transistor source is coupled to a second voltage source. The second nMOS transistor has a second-nMOS-transistor gate, source, and drain. The second-nMOS-transistor source is coupled to the second voltage source. The first-nMOS-transistor drain and the second-nMOS-transistor drain are a same drain.

Continuous diffusion configurable standard cell architecture

Method and apparatus for voltage level shifters (VLS) design in bulk CMOS technology. A multi-voltage circuit or VLS that operate with different voltage levels and that provides area and power savings for multi-bit implementation of level shifter design. A two-bit VLS to shift bits from a first voltage level logic to a second voltage level logic. The VLS formed with a first N-well in a substrate. The VLS formed with a second N-well in the substrate, adjacent to a side of the first N-well. The VLS formed with a third N-well in the substrate, adjacent to a side of the first N-well and opposite the second N-well. A first one-bit VLS circuit having a portion formed on the first N-well and a portion formed on the second N-well. A second bit VLS circuit having a portion formed on the first N-well and a portion formed on the third N-well.

Compact and robust level shifter layout design

A multimode, uniform-latency clock generation circuit (CGC) is described herein. In one example, the multimode, uniform-latency CGC generates a pulse clock signal via a clock generation path responsive to a clock chopping signal being active and generates a phase clock signal via the same clock generation path responsive to the clock chopping signal being inactive. The clock chopping signal is activated responsive to a mode control input signal being in a first state and deactivated responsive to either the mode control input signal being in a second state or a plurality of clock enable signals being inactive. In one or more embodiments, a multimode, uniform-latency CGC is included in a microprocessor for providing pulse clock signals to inter-stage pulsed sequential storage elements when operating in a timing sensitive mode and for providing phase clock signals to the inter-stage pulsed sequential storage elements when operating in a timing insensitive mode.

Multimode, uniform-latency clock generation circuit

A multi-enabled clock gating circuit reduces clock enable setup time. In one example, the multi-enabled clock gating circuit comprises an OAI logic gate and a clock enable control circuit. The OAI logic gate is configured to generate a gated clock signal by inverting an input clock signal responsive to one of a timing-sensitive clock enable signal and a timing-insensitive clock enable signal being active. The clock enable control circuit is configured to prevent the OAI logic gate from receiving the timing-insensitive clock enable signal responsive to the timing-sensitive clock enable signal being active. In one or more embodiments, a multi-enabled clock gating circuit having reduced clock enable setup time may be included in an integrated circuit for implementing clock gating during different operating modes of the integrated circuit.

Method and apparatus for reducing clock enable setup time in a multi-enabled clock gating circuit

A method and a flip-flop is disclosed in which power consumption is reduced in a standby mode. In a first aspect, the flip-flop comprises a first latch adapted to be coupled to a first power supply and a second latch coupled to the first latch and adapted to be coupled to a second power supply. The first and second power supplies are independently controllable to minimize power consumption in a standby mode. In a second aspect, a method for minimizing the power consumption of a flip-flop is also disclosed. The flip-flop includes a first latch and a second latch coupled thereto. The method comprises providing a first independently controllable power supply coupled to the master latch; and providing a second independently controllable power supply coupled to the slave latch. The method further includes reducing the voltage of at least one of the first and second power supplies responsive to the detection of a power saving mode.

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Cary, NC, United States of America

William Goodall, Iii