Eastman-kodak Company

International Business Machines Corporation

Other

Ferro Corporation

Clarkson University

William G America

Suryadevara Vijayakumar Babu

Yie-Shein Her

Ramanathan Srinivasan

Steven Hilton Johnston

David L Losee

Brian W Messenger

Kaushik Arun Kumar

Stephen L Kosman

Loretta R Fendrock

Christopher R Hoople

A structure and method for removing damages of a dual damascene structure after plasma etching. The method includes the use of sublimation processes to deposit reactive material onto the damaged regions and conditions to achieve a controlled removal of the damaged region. Furthermore a semiconductor structure includes a dual damascene structure that has been treated by the method.

Chemical oxide removal of plasma damaged SiCOH low k dielectrics

Method and apparatus for treating an edge region of a wafer. A toroidal shaped plasma cavity has an inner diameter which is slightly less than the diameter of the wafer being treated so that only the edge region of the wafer extends into the toroidal plasma cavity. An inert gas is flowed across a front and back side of the wafer into the plasma cavity. A reactive gas is flowed directly into the plasma cavity. The gases exit the plasma cavity without flowing over the surface of the wafer.

Method and apparatus for treating wafer edge region with toroidal plasma

A method for removing damages of a dual damascene structure after plasma etching is disclosed. The method comprises the use of sublimation processes to deposit reactive material onto the damaged regions and conditions to achieve a controlled removal of the damaged region. Furthermore a semiconductor structure comprising a dual damascene structure that has been treated by the method is disclosed.

A dual damascene conductor structure is formed on a substrate with an exposed conductor on top covered by a buried cap, a dielectric layer (DL) and an organic layer (OL). Form a lower via hard mask layers over the OL and form a top trench patterning hard mask over the lower, via hard mask. Form a trench pattern hole through the trench hard mask layer; and form a via pattern hole through the via hard mask layer in a region exposed below the trench pattern hole. Etch a via pattern hole into the OL and then etch a via pattern hole down into the DL. Etch away the trench pattern layer and the OL layer below the trench pattern hole. Etch the via hole through the DL exposing the cap while simultaneously partially etching the DL to a final trench depth to form a trench in the DL below the trench pattern hole, with the trench having a bottom above the cap and sidewalls in the DL.

Integrated dual damascene RIE process with organic patterning layer

A new slurry for shallow trench isolation (STI) processing in the chemical mechanical planarization (CMP) in microelectronic industry comprising an aqueous medium having an abrasive; and a compound which has a carboxylic group and an electrophilic functional group. The combination of ceria and/or titania with amino acids to obtain polishing selectivity's greater than 5:1. CMP is used for removing the excess oxide and planarizing the substrate and the trench. The silicon nitride acts as a stop layer, preventing the polishing of underlying silicon substrate.

Slurry for chemical mechanical polishing silicon dioxide

A method for implementing dual damascene processing includes forming a first hardmask layer over an interlevel dielectric layer, and forming a second hardmask layer over the first hardmask layer. A trench pattern is opened within a third hardmask layer formed over the second hardmask. A first etch process is implemented so as to define a via pattern completely through the second hardmask layer and partially through the first hardmask layer, and a second etch process is implemented to transfer the trench pattern and the via pattern into the interlevel dielectric layer.

Method for reactive ion etch processing of a dual damascene structure

The present invention relates to an aqueous slurry that is particularly useful for removing silicon dioxide in preference to silicon nitride by chemical-mechanical processing. The aqueous slurry according to the invention includes abrasive particles and an organic compound having both a carboxylic acid functional group and a second functional group selected from amines and halides. The present invention also relates to a method of removing silicon dioxide in preference to silicon nitride from a surface of an article by chemical-mechanical polishing. The method includes polishing the surface using a polishing pad, water, abrasive particles, and an organic compound having both a carboxylic acid functional group and a second functional group selected from amines and halides. The abrasive particles can be dispersed in the aqueous medium or they can be bonded to the polishing pad. The aqueous slurry and method of the present invention provide high silicon dioxide to silicon nitride removal rate selectivity over a wide range of pH, which is particularly useful for the fabrication of shallow trench isolation structures on semiconductor devices.

An image sensor, includes a semiconductor substrate; a photosensor having, a first photosensing region including a first stack of one or more layers of transparent materials overlying the substrate, the first photosensing region having a spectral response having peaks and valleys, and a second photosensing region including a second stack of one or more layers of transparent materials overlying the substrate, the second photosensing region having a spectral response having peaks and valleys; and wherein at least one peak or valley of the spectral response of the first region is matched to at least one valley or peak respectively of the spectral response of the second region such that the average spectral response of the photosensor is smoother than the individual spectral response of either the first or second photosensing regions.

Image sensor having improved spectral response uniformity

A method and apparatus of forming adjacent, non-overlapping CCD electrodes within an image sensing device such the electrodes are U-shaped. The device provided by the disclosed method employs a substrate with a gate dielectric layer formed on a surface of the substrate with a plurality of phases created within the CCD. A deposited silicon layer is placed on the surface of the CCD and a mask is used to cover areas other than the first set of electrodes. Etching takes places leaving the mask areas to the deposited silicon and a set of side walls to the remaining deposited silicon are then oxidized. A first set of electrodes by forming an electrode layer placed over the CCD. CMP is employed to remove remaining deposited silicon layer as well as portions of the electrode layer such that the side walls remain vertical portions to electrode layer remaining in the side walls. The process is then repeated by placing another electrode material layer and another CMP process leaving two sets of adjacent U-shaped gates.

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Hilton, NY, United States of America

William G America