International Business Machines Corporation

Globalfoundries Inc.

William Francis Landers

Mukta G Farooq

Charles Robert Davis

John A Griesemer

Thomas M Shaw

Adam D Ticknor

Lawrence Alfred Clevenger

Kevin Shawn Petrarca

Richard Paul Volant

David L Questad

Karl E Boggs

Kenneth M Davis

Jyothi Singh

Chih-Chao Yang

Huilong Zhu

Carl John Radens

Isaac Lauer

Timothy Dooling Sullivan

Michael F Lofaro

Ian D Melville

Kevin R Winstel

Troy Lawrence Graves-Abe

Ronald Dean Goldblatt

Donna S Zupanski-Nielsen

Michael L Passow

Dae Young Jung

Gary Lafontant

Neereja Sundaresan

Thomas R Fisher, Jr

David L Hawken

Jeffrey P Gambino

Louis L Hsu

Timothy Harrison Daubenspeck

Kirk David Peterson

Joshua T Smith

Matthew Earl Colburn

Sanjay C Mehta

Wai-Kin Li

Elbert Emin Huang

Sandra Guy Malhotra

Louis Lu-Chen Hsu

Xiao Hu Liu

Vincent James McGahay

Emily R Kinser

Roger Allan Quon

Jin Ping Liu

Thomas George Ference

Robert Hannon

Michael Wayne Lane

H Bernhard Pogge

Thomas Edward Lombardi

Eric Gerhard Liniger

Jeremy K Stephens

Matthew S Angyal

Habib Hichri

Matthew J Rutten

Brett H Engel

Scott W Crowder

Melissa Alyson Smith

Jia Lee

Andrew J Martin

Walter E Mlynko

Lloyd G Burrell

Teresa Jacqueline Wu

Michael Joseph MacDonald

Mark P Murray

Srikanth Srinivasan

Ronald D Fiege

Edward Paul Barth

Kathryn E Schlichting

Hai Pham Longworth

Thomas Edwin Sandwick

Robert M Merkling, Jr

Diana Llera-Hurlburt

Sanjit Kumar Das

Dean Allen Schaffer

Jasvir Singh Jaspal

Carol Elaine Gustafson

John Carlo Minunni, Jr

Donna S Zupanski-Nielson

Techniques regarding an embedded microstrip transmission line implemented in one more superconducting microwave electronic devices are provided. For example, one or more embodiments described herein can comprise an apparatus, which can include a superconducting material layer positioned on a raised portion of a dielectric substrate. The raised portion can extend from a surface of the dielectric substrate. The apparatus can also comprise a dielectric film that covers at least a portion of the superconducting material layer and the raised portion of the dielectric substrate.

Embedded microstrip transmission line

Microfluidic chips that can comprise thin substrates and/or a high density of vias are described herein. An apparatus comprises: a silicon device layer comprising a plurality of vias, the plurality of vias comprising greater than or equal to about 100 vias per square centimeter of a surface of the silicon device layer and less than or equal to about 100,000 vias per square centimeter of the surface of the silicon device layer, and the plurality of vias extending through the silicon device layer; and a sealing layer bonded to the silicon device layer, wherein the sealing layer has greater rigidity than the silicon device layer. In some embodiments, the silicon device layer has a thickness between about 7 micrometers and about 500 micrometers while a via of the plurality of vias has a diameter between about 5 micrometers and about 5 millimeters.

Microfluidic chips with one or more vias

A three-dimensional organic structure or glass interposer structure and methods of manufacture are disclosed. The method includes forming lined metal vias in a substrate. The method further includes removing the substrate, leaving the lined metal vias. The method further includes forming a new substrate about the lined metal vias. The method also includes connecting the lined metal vias to wiring layers using back end of the line processes.

Three dimensional organic or glass interposer

The present invention relates to bonded semiconductor integrated circuits, more specifically to a structure to protect against crack propagation into any layer of such integrated circuits. Embodiments of the present invention may include a first semiconductor substrate having a first layer bonded to second layer of a substantially thinner second semiconductor substrate by a bonding layer. The first layer may contain a crack stop. The crack stop may be in contact with a circumferential wall, made up of posts, that extends through the bonding layer, the second layer, and the second substrate.

Structure and method for making crack stop for 3D integrated circuits

A structure to prevent propagation of a crack into the active region of a 3D integrated circuit, such as a crack initiated by a flaw at the periphery of a thinned substrate layer or a bonding layer, and methods of forming the same is disclosed.

The present invention includes embodiments of a processing method, and resulting structure, for building a chip having a TSV pillar which can be used as an interconnecting structure. The process includes the deposition of a dual diffusion barrier between the TSV and the substrate the TSV is embedded within. The TSV is then exposed from the back side of the substrate so that at least a portion of the TSV protrudes from the substrate and can be used as a contact for connecting the chip to another surface. The resulting TSV is rigid, highly conductive, can be placed in a tightly pitched grid of contacts, and reduces effects of CTE mismatch.

TSV pillar as an interconnecting structure

Disclosed are a structure including alignment marks and a method of forming alignment marks in three dimensional (3D) structures. The method includes forming apertures in a first surface of a first semiconductor substrate; joining the first surface of the first semiconductor substrate to a first surface of a second semiconductor substrate; thinning the first semiconductor on a second surface of the first semiconductor substrate to provide optical contrast between the apertures and the first semiconductor substrate; and aligning a feature on the second surface of the first semiconductor substrate using the apertures as at least one alignment mark.

Alignment marks to enable 3D integration

A tool that allows three dimensional chip circuit designs to be checked subsequent to 3D design layer mirroring. The 3D chip design is converted to a corresponding 2D chip design by mirroring one or more design layers from the mirrored side of a 3D design and merging those design layers with unmirrored design layers from the unmirrored side of a 3D design. The converted circuit design can be processed by standard verification checks. The tool may also receive design layers corresponding to an integrated circuit that will pass through multiple semiconductor chips. Each design cell is examined to determine if it corresponds to a mirrored or unmirrored side of its respective semiconductor chip. If the respective design cell corresponds to the mirrored side, the design cell is mirrored. All mirrored cells are then merged with the unmirrored design cells in the correct order. The merged design is processed by standard verification checks. The tool also has the capability to create terminal metal abstracts for two adjoining chips. One of the abstracts is mirrored and then merged with the other for connectivity and alignment checking.

Circuit design checking for three dimensional chip technology

A system and method comprises depositing a dielectric layer on a substrate and depositing a metal layer on the dielectric layer. The system and method further includes depositing a high temperature diffusion barrier metal cap on the metal layer. The system and method further includes depositing a second dielectric layer on the high temperature diffusion barrier metal cap and the first dielectric layer, and etching a via into the second dielectric layer, such that the high temperature diffusion barrier metal cap is exposed. The system and method further includes depositing an under bump metallurgy in the via, and forming a C4 ball on the under bump metallurgy layer.

Structure and method to improve current-carrying capabilities of C4 joints

The embodiments provide a method for reducing electromigration in a circuit containing a through-silicon via (TSV) and the resulting novel structure for the TSV. A TSV is formed through a semiconductor substrate. A first end of the TSV connects to a first metallization layer on a device side of the semiconductor substrate. A second end of the TSV connects to a second metallization layer on a grind side of the semiconductor substrate. A first flat edge is created on the first end of the TSV at the intersection of the first end of the TSV and the first metallization layer. A second flat edge is created on the second end of the TSV at the intersection of the second end of the TSV and the second metallization layer. On top of the first end a metal contact grid is placed, having less than eighty percent metal coverage.

Enhanced electromigration resistance in TSV structure and design

The present invention relates to a method for fabricating a semiconductor device with a last level copper-to-C4 connection that is essentially free of aluminum. Specifically, the last level copper-to-C4 connection comprises an interfacial cap structure containing CoWP, NiMoP, NiMoB, NiReP, NiWP, and combinations thereof. Preferably, the interfacial cap structure comprises at least one CoWP layer. Such a CoWP layer can be readily formed over a last level copper interconnect by a selective electroless plating process.

Method for fabricating last level copper-to-C4 connection with interfacial cap structure

An electrical structure and method comprising a first substrate electrically and mechanically connected to a second substrate. The first substrate comprises a first electrically conductive pad and a second electrically conductive pad. The second substrate comprises a third electrically conductive pad, a fourth electrically conductive pad, and a first electrically conductive member. The fourth electrically conductive pad comprises a height that is different than a height of the first electrically conductive member. The electrically conductive member is electrically and mechanically connected to the fourth electrically conductive pad. A first solder ball connects the first electrically conductive pad to the third electrically conductive pad. The first solder ball comprises a first diameter. A second solder ball connects the second electrically conductive pad to the first electrically conductive member. The second solder ball comprises a second diameter. The first diameter is greater than said second diameter.

Structure and method for producing multiple size interconnections

The present invention provides a method of strengthening a structure, to heal the imperfection of the structure, to reinforce the structure, and thus strengthening the dielectric without compromising the desirable low dielectric constant of the structure. The inventive method includes the steps of providing a semiconductor structure having at least one interconnect structure; dicing the interconnect structure; applying at least one infiltrant into the interconnect structure; and infiltrating the infiltrant to infiltrate into the interconnect structure.

Strengthening of a structure by infiltration

Growing community of inventors

Wappingers Falls, NY, United States of America

William Francis Landers