Ramtron International Corporation

Hitachi, Ltd.

William F Kraus

Dennis R Wilson

Lark E Lehman

Judith E Allen

Jarrod Eliason

Donald J Verhaeghe

Yoshihiko Yasu

Steven D Traynor

A boosting circuit for a ferroelectric memory using a NAND-INVERT circuit to control one electrode of a ferroelectric boosting capacitor. The other node of the capacitor is connected to the node to be boosted, which may be coupled to a word line. The NAND circuit has two inputs, one being coupled to the word line and another for receiving a timing signal. The timing input rises to initiate the boosting operation, and falls to initiate the removal of the boosted voltage. Only the selected word line in the memory array is affected as any word line remaining at a low logic level &ldquo;0&rdquo; will keep the inverter output clamped low. A second embodiment adds a second N-channel transistor in series with the inverter's N-channel transistor to allow for the option of floating the inverter output if it is desired to more quickly drive the word line high during its first upward transition.

CMOS boosting circuit utilizing ferroelectric capacitors

A memory cell layout for use in a,T/,C ferroelectric memory array includes an access transistor having a gate coupled to a word line and a current path coupled between a bit line and an internal cell node, a shunt word line extending across the memory cell that is electrically isolated from the word line and the access transistor within the physical boundary of the memory cell, and a ferroelectric capacitor coupled between the internal cell node and a plate line.

Reference cell configuration for a 1T/1C ferroelectric memory

A memory cell layout for use in a 1T/1C ferroelectric memory array includes an access transistor having a gate coupled to a word line and a current path coupled between a bit line and an internal cell node, a shunt word line extending across the memory cell that is electrically isolated from the word line and the access transistor within the physical boundary of the memory cell, and a ferroelectric capacitor coupled between the internal cell node and a plate line.

Memory cell configuration for a 1T/1C ferroelectric memory

A non-volatile ferroelectric latch includes a sense amplifier having at least one input/output coupled to a bit-line node, a ferroelectric storage capacitor coupled between a plate-line node and the bit-line node, and a load element coupled to the bit-line node. The sense amplifier further includes a second input/output coupled to a second bit-line node and the latch further includes a second ferroelectric storage capacitor coupled between a second plate-line node and the second bit-sine node, and a second load element coupled to the second bit-line node. The load element includes a dynamic, switched ferroelectric capacitor a static, nonswitched ferroelectric capacitor, a linear capacitor, or even a resistive load.

Ferroelectric non-volatile latch circuits

A preferred state power-up latch circuit includes first and second cross-coupled P-channel transistors coupled to a first source of supply voltage, first and second cross-coupled N-channel transistors coupled to a second source of supply voltage, the transistors being coupled together to form a latch having an output node, in which at least one of the gate lengths is unequal to the other gates lengths in order to establish a preferred state upon power-up, and the gate width of all the transistors is equal.

CMOS preferred state power-up latch

A plate line segmentation scheme for a 1T/1C ferroelectric memory architecture includes an array of 1T/1C ferroelectric memory cells, word lines corresponding to each row of 1T/1C ferroelectric memory cells, and plate lines corresponding to each row of 1T/1C ferroelectric memory cells, wherein each plate line is divided into two or more equal plate line segments, only one of which is driven when a corresponding word line is selected.

Plate line segmentation in a 1T/1C ferroelectric memory

A reference cell layout for use in a 1T/1C ferroelectric memory array includes a transistor of a first polarity type having a gate coupled to a reference word line and a current path coupled between a bit line and an internal cell node, a transistor of a second polarity type having a gate coupled to a pre-charge line and a current path coupled between a source of power supply voltage and the internal cell node, a shunt reference word line extending across the reference cell that is electrically isolated from the reference word line, the pre-charge line and the transistors within the physical boundary of the memory cell, and a ferroelectric capacitor coupled between the internal cell node and a reference plate line.

A method of driving a selected plate line segment in a 1T/1C memory, the method including the steps of logically combining an odd word line signal and an even word line signal to form a first logic signal, logically combining the first logic signal with a plate clock signal to form a second logic signal, latching the second logic signal, and driving the selected plate line segment with the latched second logic signal.

Plate line driver circuit for a 1T/1C ferroelectric memory

A reference cell for a 1T/1C ferroelectric memory includes a transistor of a first polarity type having a gate coupled to a reference cell word line, and a current path coupled between a bit line and an internal reference cell node, a transistor of a second polarity type having a gate coupled to a pre-charge line, and a current path coupled between a source of supply voltage and the internal reference cell node, and a ferroelectric capacitor coupled between the internal reference cell node and ground.

Reference cell for a 1T/1C ferroelectric memory

A cross-coupled sense amplifier includes a voltage-compensating balancing resistor serially connected between the drain of one of the P-channel transistors in the sense amplifier and the corresponding sensing/bit line node. The value of the balancing resistor is optimized so that the voltage imbalance between the P-channel transistor is minimized and sense amplifier sensitivity is maximized. A balancing resistor can also be placed in the N-channel transistors in the sense amplifier if desired. The balancing resistor in a typical application is about 100 to 200 ohms and fabricated from polysilicon.

Sense amplifier utilizing a balancing resistor

A method of operating a 1T/1C ferroelectric memory having a memory cell coupled to a word line, a bit line, and a plate line, includes the steps of turning on the word line, energizing the plate line to establish a charge on the bit line, turning off the word line, and sensing the charge on the bit line while the word line is off.

Sensing methodology for a 1T/1C ferroelectric memory

A power-on detect circuit includes: a resistor divider having a first node, a second node coupled to ground, and a center tap; a bandgap circuit for providing a reference voltage; a differential amplifier having a first input for receiving the reference voltage, a second input coupled to the center tap of the bandgap reference voltage circuit, and an output for providing a power-on detect signal; and a suppression circuit for coupling the first node of the resistor divider to a source of supply voltage once the reference voltage substantially achieves a stable reference voltage level. The suppression circuit has an input for receiving a trigger voltage generated in the bandgap circuit, and an output coupled to the first node of the resistor divider. The suppression circuit includes: an input section having an input for receiving the trigger voltage, and an output; a switch coupled between the source of supply voltage and the first node of the resistor divider having a control node coupled to the output of the input section; and a capacitor coupled to the control node of the switch. Both the switch and the bandgap circuit are responsive to the power-on detect signal for further reducing power consumption.

Bandgap reference based power-on detect circuit including a suppression

Bandgap reference based power-on detect circuit including a supression

A test mode circuit for an integrated circuit includes a high voltage detector having an input for receiving a high voltage signal, a Schmitt trigger having an input coupled to the output of the high voltage detector, a latch having an input coupled to the output of the Schmitt trigger and an output for providing a test mode signal in a test operational mode, and additional control circuitry for disabling the high voltage detector and Schmitt trigger so that substantially all of the active current flow in the high voltage detector and Schmitt trigger is eliminated in a normal operational mode. The test mode circuit further includes circuitry for preventing a reset condition in the latch during the test mode until a power-down condition occurs. A glitch filter is also included, which is interposed between the output of the Schmitt trigger and the input to the latch. An integrated circuit pin is coupled to both the test mode circuit and to other circuitry on the integrated circuit not forming part of the test mode circuit.

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Colorado Springs, CO, United States of America

William F Kraus