Advanced Micro Devices Corporation

Spansion Llc.

Fujitsu Limited (japan)

William F Kern

Stephan Rosner

Stephen T Novak

Ralf Flemming

Matthias Baer

Matthew James Fischer

James D Cummins

Bradley E Thomson

Peter Chan

Duong X Dinh

Methods and systems are herein disclosed for write operation retry using the data stored and retained in an internal buffer within the non-volatile memory device. By using the data stored in the internal buffer, the systems and method of the present invention eliminate the need to include a dedicated retry buffer at the system level. Thereby, reducing the system cost, minimizing space consumption on a board within the system and, in some instance, limiting the latency attributed to a retry that relies on retrying the write based on re-transferring of the data contents to the internal non-volatile memory buffer.

Retargeting of a write operation retry in the event of a write operation failure

Systems and/or methods that provide for frequency distributed flash memory allocation are disclosed. The systems and methods determine the rate at which a system address is being written and the current erase cycle state of each data block in the non-volatile memory device and assigns a physical address to the write operation based on the determined system address rate and the current erase state of each data block in the non-volatile system. In this regard, system addresses that are assigned more frequently are assigned physical page addresses from data blocks which have a low erase cycle state (i.e., greater cycle endurance remaining) and system addresses that assigned less frequently are assigned physical page addresses from data blocks which have a high erase cycle state (i.e., lesser cycle endurance remaining). The result is a more robust non-volatile device having increased erase/initialization cycle endurance, which adds to the overall reliability of the device over time.

Frequency distributed flash memory allocation based on free page tables

Systems and/or methods are presented that provide for recording transactions that occur during a write process for the purpose of recovering the transactions in the event of a power loss. In an aspect a system implements an organization that reflects a cache architecture that is organized according to the cache way and set index of each transaction In this regard, the cache way and set index cache architecture provides for a post-power loss search operation that is limited to identifying duplicate locations within the cache-line and keeping only the most recent modification. Thus the system provides pre-organization in terms of self-aggregation by cache way and set index recording that facilitates cache-line eviction processing in the event that the cache is determined to be full.

Translation table coherency mecahanism using cache way and set index write buffers

An acceleration mechanism for boot-up processing in a computing system is provided. The acceleration mechanism relies on recording most, if not all, of the read transactions, associated with requests and retrievals made during a boot-up and, in some aspects most, if not all, of the write transactions, associated with requests and stores made during a shutdown process. Prior to executing the boot-up process, data associated with the transactions is pre-fetched based on the recorded information and used to make the requests or information retrievals during the ensuing boot-up process. Additionally, since the mechanism of the present innovation provides for continual recording and the transaction data, the acceleration of the boot-up process can be adaptive even if hardware additions/changes or any other changes that affect the boot-up or shutdown process occur.

Adaptive system boot accelerator for computing systems

A wireless computer system () is formed to have a host section () and a wireless hardware section (). A first portion of a transmission frame is formed in system memory () of a host section () and a second portion of the transmission frame is formed in the wireless hardware section (). The wireless hardware section () begins transmitting the first transmission frame portion while downloading the second transmission frame portion from the system memory () into the wireless hardware section ().

Wireless computer system with queue and scheduler

A wireless computer system () is formed to have a host section () and a wireless hardware section (). A first portion of a transmission frame is formed in system memory () of a host section () and a second portion of the transmission frame is formed in the wireless hardware section (). The wireless hardware section () begins transmitting the first transmission frame portion while downloading the second transmission frame portion from the system memory () into the wireless hardware section (). Bus latencies are masked by at least overlapping transmitting the first portion of the transmit frame while downloading the second portion.

Wireless computer system with latency masking

A compact low-power radio frequency (RF) transceiver with a built-in antenna provides wireless communication between a computer and another device. A direct conversion receiver together with a voltage controlled oscillator, phase lock loop circuits, digitally controlled divider circuits and a patch antenna are packaged into a compact enclosure, having dimensions within the PCMCIA format. In some embodiments, the transceiver enters a sleep mode whenever it is idle in order to further conserve power. In other embodiments, a signature detector enables the transceiver to distinguish between noise and valid messages by recognizing a signature word embedded in the data packet.

Radio tranceiver for data communications

A station in the WLAN monitors each transmitted frame to determine whether the frame transmission was protected by an existing outstanding airtime reservation. If a frame is transmitted without an airtime reservation and no response frame is received, the station assumes that the transmission failed due to contention, and monitors the number of contention attempts made to transmit each frame, and the number of failures to receive an acknowledgement. Based on this information, the station dynamically adjusts an RTS/CTS threshold used to determine whether or not an RTS/CTS exchange mechanism should be enabled. If a frame is transmitted during a time interval protected by an outstanding airtime reservation and no response frame is received, the station assumes that the transmission failed due to a bit error, and monitors the number of bit error rate (BER) attempts made to transmit each frame, and the number of BER failures to receive an acknowledgement. Based on this information, the station dynamically adjusts a fragmentation threshold used to determine whether or not a data frame fragmentation mechanism should be enabled.

Growing community of inventors

Palo Alto, CA, United States of America

William F Kern