Hughes Aircraft Company

Hughes Electronics Corporation

The Directv Group, Inc.

William E Stanchina

Madjid Hafizi

Robert A Metzger

David B Rensch

Lawrence M Burns

Marion D Clark

K Vaidyanathan

Daniel Yap

Lawrence E Larson

Cheng P Wen

Chan-Shin Wu

Julia J Brown

Loi D Nguyen

Thomas C Hasenberg

Mark Lui

William W Hooper

April S Brown

Daniel Docter

Cheng-Keng Pao

Loren G McCray

Joseph A Henige

Thomas Hasenberg

An optoelectronic device has an epitaxial layer structure that has a substrate and a first layer formed adjacent to the substrate. The first layer may, for example, form a contact layer. A second layer is formed adjacent to the first layer. The second layer forms a selectively optically varying layer, so that during a first state the second layer is optically absorbing and during a second state the layer is optically transparent. A third layer is formed adjacent to the second layer. A fourth layer is formed adjacent to the third layer. The fourth layer is an optically transparent layer. An optoelectronic device and an electronic device may be formed on the same substrate that share the same layers. The layers used depends upon the devices formed.

Multi-function optoelectronic device structure

An integrated circuit technology combines heterojunction bipolar transistors (HBTs), high electron mobility transistors (HEMTs) and other components along with interconnect metallization on a single substrate. In a preferred embodiment a flat substrate is patterned, using dry etching, to provide one or more mesas in locations which will eventually support HEMTs. A device stack including HEMT and HBT layers is built up over the substrate by molecular beam epitaxy, with the active HEMT devices located on the mesas within openings in the HBT layer. In this way the active HEMT is aligned with the HBT layer to planarize the finished integrated circuit.

Method for making integrated heterojunction bipolar/high electron

The number of input latching comparators in a flash analog-to-digital converter is significantly reduced by merging the input latching function into exclusive OR gates used in the converter's decoding section. A latching exclusive OR gate used for this purpose employs resonant tunneling diodes as the latching devices, with hysteresis and impedance elements connected to ensure that the gate latches in a logic state that corresponds to the input analog signal. The latching logic gates operate in a current mode, enabling updated logic states to be latched in response to a periodic clock signal.

Flash analog-to-digital converter with latching exclusive or gates

A submicron emitter heterojunction bipolar transistor and a method for fabricating the same is disclosed. The fabrication process includes lattice matched growth of subcollector, collector, base, emitter, and emitter cap layers in sequential order on a semi-insulating semiconductor substrate. An emitter cap mesa, an emitter/base/collector mesa and a subcollector mesa are formed. Dielectric platforms are formed extending the base/collector layers laterally. Sidewalls are formed on the sides of emitter cap mesa and the sides of the extended base/collector layers and undercuts are etched into the emitter layer and the upper portion of the subcollector layer. This forms an overhang on the emitter cap mesa with respect to the emitter layer and an overhang on the base/collector layers with respect to the upper portion of the subcollector layer. Emitter, base and collector contacts are simultaneously formed, the base contact aligned to the edge of the emitter cap overhang and the collector contact aligned to the edge of the base/collector layer overhang.

Method for making fully self-aligned submicron heterojunction bipolar

A multi-layer collector heterojunction transistor (10) provides for high power, high efficiency transistor amplifier operation, especially in the RF (radio frequency) range of operation. A larger band gap first collector layer (12), approximately 15% of the active collector region (11) thickness, is provided at the base-collector junction (13). A smaller band gap second collector layer (14) forms the remainder of the active collector region (11). The multi-layer collector structure provides higher reverse bias breakdown voltage and higher carrier mobility during relevant portions of the output signal swing. A lower saturation voltage limit, or 'knee' voltage, is provided at the operating points where linear operating regions transition to saturation operating regions as depicted in the output voltage-current (I-V) characteristic curves. The magnitude of the output signal swing of an amplifier may be increased, providing higher power amplification with greater power efficiency. The power supply voltage for the amplifier may be increased, providing for the use of a smaller, lighter power supply.

Multi-layer collector heterojunction transistor

A high speed diode with a low forward-bias turn-on voltage is formed by a heterojunction between a layer of doped semiconductor material that has a narrow bandgap energy of not more than about 0.4 eV, and a layer of oppositely doped semiconductor material that has a substantially wider bandgap energy. The device operates with a lower turn-on voltage than has previously been attainable, despite lattice mismatches between the two materials that can produce strain and substantial lattice dislocations in the low bandgap material. The two materials are selected so that the valence and conduction band edge discontinuities at the heterojunction enable a forward carrier flow but block a reverse carrier flow across the junction under forward-bias conditions. Preferred material systems are InAs for the narrow bandgap material, InGaAs for the wider bandgap material and InP for the substrate, or AlSb for the wider bandgap material and GaSb for the substrate. A compositional grading can be provided at the heterojunction to reduce energy band spikes, and a region of low dopant concentration is included in the wider bandgap material to increase the diode's reverse-bias breakdown voltage.

Heterojunction diode with low turn-on voltage

A photoresist process combined with wet chemical etching and silicon oxide evaporation and self-aligned lift-off is used to reduce the parasitic (extrinsic) base-collector junction capacitance (C.sub.BC) of InP-based heterojunction bipolar transistors (HBTs). At least a portion of the mesa related to the base contact is etched around the intrinsic device area and then back-filled with evaporated oxide. The base contact pad is then formed over the back-filled oxide, thus reducing the extrinsic device area. This process provides a self-aligned etching of a mesa and deposition and lift-off of the back-fill oxide in one single photoresist processing step. The process is simple and reproducible and provides very high yield. It also eliminates the need for costly and complicated dry-etching techniques.

Reduction of base-collector junction parasitic capacitance of

An electrical junction is precisely located between a highly p doped semiconductor material and a more lightly n doped semiconductor material by providing a lightly p doped buffer region between the two materials, with a doping level on the order of the n doped material's. The buffer region is made wide enough to establish an electrical junction at approximately its interface with the n doped material, despite a diffusion of dopant from the p doped material. When applied to a heterojunction bipolar transistor (HBT), the transistor's base serves as the heavily p doped material and its emitter as the more lightly n doped material. The buffer region is preferably employed in conjunction with a graded superlattice, located between the buffer and emitter, which inhibits dopant diffusion from the base into the emitter. A p-n junction is formed within the superlattice, which functions on one side as an electrical extension of the emitter and on the other side as an electrical extension of the buffer, and establishes the electrical junction at the p-n junction location. The precise positioning of the electrical junction results in a known and repeatable emitter-base turn-on voltage.

Electrical junction device with lightly doped buffer region to precisely

A gain-stable npn heterojunction bipolar transistor includes a graded superlattice between its base and emitter consisting of multiple discrete periods, with each period having a layer of base material and another layer of emitter material. The thicknesses of the base material layers decrease while the thicknesses of the emitter material layers increase in discrete steps for each successive period from the base to the emitter. The thickness of each period is preferably at least about 20 Angstroms, with the superlattice including more than five periods. The superlattice is preferably doped to establish an electrical base-emitter junction at a desired location. The graded superlattice inhibits the diffusion of beryllium p dopant from the base into the emitter during transistor operation, thus stabilizing the device's gain and turn-on voltage.

Gain-stable NPN heterojunction bipolar transistor

A heterojunction bipolar transistor (HBT) (10,30) includes an indium-gallium-arsenide (InGaAs), indium-phosphide (InP) or aluminum-indium-arsenide (AlInAs) collector layer (14) formed over an indium-phosphide (InP) substrate (12). A base layer (16,32) including gallium (Ga), arsenic (As) and antimony (Sb) is formed over the collector layer (14), and an AlInAs or InP emitter layer (18) is formed over the base layer (16,32). The base layer may be ternary gallium-arsenide-antimonide (GaAsSb) doped with beryllium (Be) (16), or a strained-layer-superlattice (SLS) structure (32) including alternating superlattice (32b,32a) layers of undoped gallium-arsenide (GaAs) and P-doped gallium-antimonide (GaSb). The GaSb superlattice layers (32a) are preferably doped with silicon (Si), which is much less diffusive than Be.

NPN heterojunction bipolar transistor including antimonide base formed

A donor layer (17) including an undoped wide bandgap material (14) and an n-type dopant (16) is deposited on a substrate (12) by molecular beam epitaxy (MBE) at a first temperature which is high enough for optimal growth of the donor layer (17). The dopant (16) is silicon or another material which exhibits surface segregation in the wide bandgap material (14) at the first temperature. An undoped spacer layer (18) of the wide bandgap material is deposited on the donor layer (17) at a second temperature which is sufficiently lower than the first temperature that surface segregation of the dopant material from the donor layer (17) into the spacer layer (18) is substantially suppressed. A channel layer (20) of a narrow bandgap material is formed on the spacer layer (18) at a third temperature which is higher than the second temperature and selected for optimal growth of the channel layer (20). The spacer layer (18) is substantially undoped, and the low temperature growth and reduction of donor movement reduces ionized impurity scattering in the channel layer (20).

Method of fabricating inverted modulation-doped heterostructure

A heterojunction bipolar transistor (HBT) is formed with self-aligned base-emitter and base-collector junctions by forming a two-level mask over a doped base layer, sequentially forming openings in registration through the two mask layers, and using the opening in one mask layer to define the collector region and the opening in the other mask layer to define the emitter. A buried conductive layer formed by a dopant implant establishes an electrical contact to the collector region, and connects to the surface via another conductive implant that extends through a lateral extension of the collector region. The collector region itself is formed by a dopant implant, while the active base region which forms junctions with the emitter and collector is thinner than the remainder of the base layer; the latter feature reduces the resistivity associated with connections to lateral base contacts. Parasitic capacitances are minimized when the collector and buried conductive layers are implanted into a semi-insulating substrate such that only the active junction regions overlap.

Self-aligned, planar heterojunction bipolar transistor

A heterojunction bipolar transistor (HBT) is formed with self-aligned base-emitter and base-collector junctions by forming a two-level mask over a doped base layer, sequentially forming openings in registration through the two mask layers, and using the opening in one mask layer to define the collector region and the opening in the other mask layer to define the emitter. A buried conductive layer formed by a dopant implant establishes an electrical contact to the collector region, and connects to the surface via another conductive implant that extends through a lateral extension of the collector region. The collector region itself is formed by a dopant implant, while the active base region which forms junctions with the emitter and collector is thinner than the remainder of the base layer; the latter feature reduces the resistivity associated with connection to lateral base contacts. Parasitic capacitances are minimized when the collector and buried conductive layers are implanted into a semi-insulating substrate such that only the active junction regions overlap.

Self-aligned, planar heterojunction bipolar transistor and method of

A depression is formed by mesa etching or the like in the surface of an insulative substrate. A first semiconductive layer structure such as a PNP layer structure is formed on the surface including the depression. An electrically insulative isolation layer is formed on the first layer structure, and then a second layer structure such as an NPN layer structure is formed on the isolation layer. The area over the depression is then masked, and the second layer structure and isolation layer are etched away from the first layer structure over areas of the surface external of the depression. Where the thicknesses of the first and second layer structures are equal, and the depth of the depression is equal to the combined thicknesses of the first layer structure and the isolation layer, the second layer structure laterally external of the depression will be coplanar with the first layer structure over the depression. Dissimilar microelectronic devices such as complementary heterojunction bipolar transistors may be formed in the exposed surfaces of the first and second layer structures respectively by common and simultaneous processing.

Growing community of inventors

Thousand Oaks, CA, United States of America

William E Stanchina