Freescale Semiconductor,inc.

North Star Innovations Inc.

William D Darlington

James Edward Vasek

Mehul D Shroff

Mark Douglas Hall

Stanley Michael Filipiak

Jonathan L Cobb

Cesar M Garza

Jinmiao James Shen

Brian J Fisher

Vikas R Sheth

A method for reducing line edge roughness (LER) in a layer of photoresist is provided. In accordance with the method, a layer of photoresist is applied to a substrate. The layer of photoresist is then patterned and annealed in an atmosphere comprising at least one gas selected from the group consisting of hydrogen, nitrogen and fluorine-containing materials. Preferably, the anneal is performed after patterning the photoresist, but either immediately after, or subsequent to, the trim.

Treatment for reduction of line edge roughness

A semiconductor device is made by patterning a conductive layer for forming gates of transistors. The process for forming the gates has a step of patterning photoresist that overlies the conductive layer. The patterned photoresist is trimmed so that its width is reduced. Fluorine, preferably F, is applied to the trimmed photoresist to increase its hardness and its selectivity to the conductive layer. Using the trimmed and fluorinated photoresist as a mask, the conductive layer is etched to form conductive features useful as gates. Transistors are formed in which the conductive pillars are gates. Other halogens, especially chlorine, may be substituted for the fluorine.

Method of making a semiconductor device using treated photoresist

Growing community of inventors

Austin, TX, United States of America

William D Darlington