Marvell International Limited

Marvellworld Trade Ltd.

Marvell Israel (misl) Ltd.

William B Weiser

Mark David Montierth

Lyman Leonard Hall

Thomas G Warner

Randall Don Briggs

Phillip H Salvatori

Jay Russell Shoen

Dan Azeroual

J Daren Bledsoe

Greg L Allen

Walter Lee McNall

Jeffrey S James

Tony R Uranga

Haggai Telem

Davey N Skinner

Eran Maor

Warren Miller

A ball grid array (BGA) package for an integrated circuit device includes an integrated circuit device having a plurality of terminals, and two largest dimensions that define a major plane. A package substrate material encloses the integrated circuit device, and is formed, in a plane parallel to the major plane, into a polygon having at least five sides. An array of contacts on an exterior surface of the package substrate material is electrically coupled to the plurality of terminals. Contacts in the array of contacts are distributed in a pattern of contact positions, and the center of each contact position may be separated from the center of each nearest other position by a separation distance that is identical throughout the pattern. Each position may be occupied by a contact, or positions in a sub-pattern may lack a contact and may be available for insertion of at least one via.

Polygonal BGA semiconductor package

Embodiments of the present disclosure provide a method that includes forming a wireless module on a first region of a circuit board and forming a host controller module on a second region of the circuit board. The method also includes forming, on the circuit board, a perforation along a boundary that separates the first region from the second region. The method further includes forming a plurality of first trace structures in the first region and forming a plurality of second trace structures in the second region, wherein each second trace structure of the plurality of second trace structures is electrically coupled to a corresponding first trace structure of the plurality of first trace structures. The method also includes disposing a tri-state contact in the second region.

Method of manufacturing an on-board wireless module architecture

In line smart print module

Some of the embodiments of the present disclosure provide a method comprising: receiving, by a peripheral device, a file for printing; transmitting, by the peripheral device to a server, the file in order to enable the server to render the file in a format that can be printed by the peripheral device; based on transmitting the file to the server, receiving, by the peripheral device from the server, (i) the file rendered in the format that can be printed by the peripheral device, and (ii) an advertisement; printing, by the peripheral device, the file rendered in the format that can be printed by the peripheral device; and displaying the contents of the advertisement on a display of the peripheral device.

Method and apparatus for remotely rendering a file in a format appropriate for printing

Embodiments of the present disclosure provide an assembly comprising circuitry of a wireless module disposed on a first region of a circuit board, and circuitry of a host controller module disposed on a second region of the circuit board. The first region is removably coupled to the second region.

On board wireless module architecture

The present disclosure describes techniques for scalable embedded memory programming. In some aspects data is received at a first communication interface from a host device, at least a portion of the data is stored to a memory device supported by a printed circuit board, and the data is transmitted to a target device via a second communication interface.

Programming target devices via traces that traverse a structurally compromised region of a printed circuit board (PCB)

Some of the embodiments of the present disclosure provide a semiconductor package structure comprising a leadframe; an interposer disposed on the leadframe, the interposer comprising a plurality of dielectric layers including at least (i) a first dielectric layer and (ii) a second dielectric layer; a semiconductor device disposed on the interposer; and a capacitor that is embedded within the interposer, wherein the capacitor is formed using at least (i) a first conductive area disposed on the first dielectric layer and (ii) a second conductive area disposed on the second dielectric layer. Other embodiments are also described and claimed.

Interposer based capacitors for semiconductor packaging

Programming target devices via traces that traverse a structurally compromised region of a printed circuit board (pcb)

Aspects of the disclosure provide an integrated circuit (IC) chip. The IC chip includes core circuits having an operational mode and a power saving mode, and at least a pad module. The pad module includes a pad, a switchable pull-up module configured to pull up a voltage on the pad when the switchable pull-up module is switched on, a switchable pull-down module configured to pull down the voltage on the pad when the switchable pull-down module is switched on, and a control module configured to control the switchable pull-up module and the switchable pull-down module according to a detection of the voltage on the pad when the core circuits enter the power saving mode.

Low power pad

A system and method are disclosed for modifying the capabilities and functions of a printer after it is manufactured. A consumable/replaceable printer cartridge includes a storage device having updated and/or additional printer function data and other data for use by the printer control circuitry to execute printer functions and other types of functions. In addition, when the printer cartridge is installed in the printer the storage device may be utilized by the printer control circuitry as expanded memory for use in executing the updated and/or additional printer functions and other types of functions.

Smart printer cartridge

An integrated circuit has operational circuitry to perform an operation. An operational regulator regulates an operating condition of the operational circuitry. The operational regulator has a sample clock to generate a sample clock signal. The sample clock signal correlates to a manufacturing variation of the electronic circuitry. The operational regulator also includes a configurator to evaluate the sample clock signal and generate a configuration signal according to the evaluation. A controller is provided to receive the configuration signal and control an operating condition of the operational circuitry according to the configuration signal.

Growing community of inventors

Meridian, ID, United States of America

William B Weiser