International Business Machines Corporation

Tokyo Electron Limited

Siemens Aktiengesellschaft

Wesley Charles Natzle

Chienfan Yu

Hussein Ibrahim Hanafi

Merritt Funk

Renee Tong Mo

David V Horak

Richard Stephan Wise

Diane Catherine Boyd

Richard L Kleinhenz

Bruce Bennett Doris

Naim Moumen

Daniel Joseph Prager

Sadanand Vinayak Deshpande

Marc Waine Cantell

Brian L Tessier

Toshiharu Furukawa

Ravikumar Ramachandran

Siddarth A Krishnan

Meikei Ieong

Hiroyuki Akatsu

Hongwen Yan

Louis DeWolf Lanzerotti

Ryan Wayne Wuthrich

Shwu-Jen Jeng

Effendi Leobandung

Steven J Holmes

Jeffrey W Sleight

Vijay Narayanan

Kevin K Chan

Ying Di Zhang

Judson Robert Holt

Timothy Joseph Dalton

Michael Patrick Chudzik

Lee Chen

Laertis Economikos

Unoh Kwon

Huiming Bu

Richard Anthony Conti

Anthony I Chou

David Edward Kotecki

Huajie Chen

William K Henson

Leathen Shi

Ashima B Chakravarti

Siddhartha Panda

Radha Sundararajan

Rangarajan Jagannathan

Rashmi Jha

David C Ahlgren

Ricky S Amos

Michael Ray Sievers

Len Yuan Tsou

Kevin Lally

Karl Paul Muller

Jeffrey J Brown

Martin Gutsche

Wei He

Chien Yu

Jack Allan Mandelman

Kirk David Peterson

Herbert Lei Ho

Dirk Pfeiffer

Tze-Chiang Chen

Gary Bela Bronner

Kathryn Turner Schonenberg

George D Papasouliotis

Steven G Barbee

Katherina E Babich

Scott David Halle

H Bernhard Pogge

Seshadri Subbanna

Robert B Laibowitz

Arpan Pravin Mahorowala

Ying Li

Thomas Safron Kanarsky

Xi Li

Robert J Purtell

Erick G Walton

Ricardo Alves Donaton

Basanth Jagannathan

Joyce C Liu

Asao Yamashita

Peter Richard Duncombe

Scott W Crowder

Hung Y Ng

Qingyun Yang

Jin J Wu

Paul William Pastel

Thomas H Ivers

Akihisa Sekiguchi

William M Chu

Patricia A O'Neil

Kevin E Mello

Kevin Augustine Pinto

Steven M Ruegsegger

Kerry L Batdorf

Derek Chen

Frederick William Buehrer

Babar A Kanh

Bidan Zhang

A transistor is provided that includes a silicon layer with a source region and a drain region, a gate stack disposed on the silicon layer between the source region and the drain region, an L shaped gate encapsulation layer disposed on sidewalls of the gate stack, and a spacer disposed above the horizontal portion of the gate encapsulation layer and adjacent to the vertical portion of the gate encapsulation layer. The gate stack has a first layer of high dielectric constant material, a second layer comprising a metal or metal alloy, and a third layer comprising silicon or polysilicon. The gate encapsulation layer has a vertical portion covering the sidewalls of the first, second, and third layers of the gate stack and a horizontal portion covering a portion of the silicon layer that is adjacent to the gate stack.

High-k/metal gate transistor with L-shaped gate encapsulation layer

A method of selectively forming a germanium structure within semiconductor manufacturing processes removes the native oxide from a nitride surface in a chemical oxide removal (COR) process and then exposes the heated nitride and oxide surface to a heated germanium containing gas to selectively form germanium only on the nitride surface but not the oxide surface.

Selective deposition of germanium spacers on nitride

Methods for fabricating gate electrode/high-k dielectric gate structures having an improved resistance to the growth of silicon dioxide (oxide) at the dielectric/silicon-based substrate interface. In an embodiment, a method of forming a transistor gate structure comprises: incorporating nitrogen into a silicon-based substrate proximate a surface of the substrate; depositing a high-k gate dielectric across the silicon-based substrate; and depositing a gate electrode across the high-k dielectric to form the gate structure. In one embodiment, the gate electrode comprises titanium nitride rich in titanium for inhibiting diffusion of oxygen.

High-k dielectric gate structures resistant to oxide growth at the dielectric/silicon substrate interface and methods of manufacture thereof

A semiconductor structure is fabricated with reduced gate capacitance by thinning of a gate electrode to provide a reduced thickness gate electrode. The gate electrode is thinned after forming a spacer layer adjoining the gate electrode. In addition, the height of the spacer layer may also be reduced. The spacer layer thus has an enhanced horizontal width desired for locating an intrinsic source/drain with respect to an extension region and in particular, an enhanced horizontal width relative to the spacer height. The reduced thickness gate electrode may be fully silicided to provide decreased gate resistance. A raised source/drain layer may be located upon the intrinsic source/drain region. The raised source/drain layer may have a top surface higher than the reduced thickness gate electrode. In addition, the raised source/drain layer may have a top surface higher than the reduced height spacer layer.

Field effect device with reduced thickness gate

A chemical composition and method for providing uniform and consistent etching of gate stacks on a semiconductor wafer, whereby the composition includes an etchant and an added ballast gas added. The gate stacks are formed using this combined etchant and ballast gas composition. The ballast gas may either be similar to, or the equivalent of, a gaseous byproduct generated within the processing chamber. The ballast gas is added in either an overload amount, or in an amount sufficient to compensate for varying pattern factor changes across the water. This etchant and added ballast gas form a substantially homogeneous etchant across the entire wafer, thereby accommodating for or compensating for these pattern factor differences. When etching the wafer using this homogeneous etchant, a passivation layer is formed on exposed wafer surfaces. The passivation layer protects the lateral sidewalls of the gate stacks during etch to result in straighter gate stacks.

Addition of ballast hydrocarbon gas to doped polysilicon etch masked by resist

In one embodiment, the present invention provides a method of fabricating a semiconducting device that includes providing a substrate including at least one semiconducting region and at least one oxygen source region; forming an oxygen barrier material atop portions of an upper surface of the at least one oxygen region; forming a high-k gate dielectric on the substrate including the at least one semiconducting region, wherein oxygen barrier material separates the high-k gate dielectric from the at least one oxygen source material; and forming a gate conductor atop the high-k gate dielectric.

Structure and method to control oxidation in high-k gate structures

Disclosed are embodiments of a MOSFET with defined halos that are bound to defined source/drain extensions and a method of forming the MOSFET. A semiconductor layer is etched to form recesses that undercut a gate dielectric layer. A low energy implant forms halos. Then, a COR pre-clean is performed and the recesses are filled by epitaxial deposition. The epi can be in-situ doped or subsequently implanted to form source/drain extensions. Alternatively, the etch is immediately followed by the COR pre-clean, which is followed by epitaxial deposition to fill the recesses. During the epitaxial deposition process, the deposited material is doped to form in-situ doped halos and, then, the dopant is switched to form in-situ doped source/drain extensions adjacent to the halos. Alternatively, after the in-situ doped halos are formed the deposition process is performed without dopants and an implant is used to form source/drain extensions.

Metal oxide field effect transistor with a sharp halo

The present invention provides a semiconducting device including a substrate including at least one semiconducting region and isolation regions; a gate structure atop the substrate having a gate dielectric layer positioned on the semiconducting region and a metal layer atop the gate dielectric layer, the gate structure having a width equal to or greater than the width of the at least one semiconducting region; and a contact structure including a base having a first width equal to the width of the gate structure and an upper surface having a second width, wherein the first width is greater than the second width. In one embodiment, the contact structure includes a polysilicon conductor and dielectric spacers, wherein each spacer of the dielectric spacer abuts a sidewall of the polysilicon conductor. In another embodiment, the contact structure includes a polysilicon conductor having a tapered sidewall.

Subgroundrule space for improved metal high-k device

A method of processing a wafer is presented that includes creating a pre-processing measurement map using measured metrology data for the wafer including metrology data for at least one isolated structure on the wafer, metrology data for at least one nested structure on the wafer, or mask data. At least one pre-processing prediction map is calculated for the wafer. A pre-processing confidence map is calculated for the wafer. The pre-processing confidence map includes a set of confidence data for the plurality of dies on the wafer. A prioritized measurement site is determined when the confidence data for one or more dies is not within the confidence limits. A new measurement recipe that includes the prioritized measurement site is then created.

Dynamic metrology sampling with wafer uniformity control

A method of monitoring a dual damascene procedure that includes calculating a pre-processing confidence map for a damascene process, the pre-processing confidence map including confidence data for a first set of dies on the wafer. An expanded pre-processing measurement recipe is established for the damascene process when one or more values in the pre-processing confidence map are not within confidence limits established for the damascene process. A reduced pre-processing measurement recipe for the first damascene process is established when one or more values in the pre-processing confidence map are within confidence limits established for the damascene process.

Dynamic metrology sampling for a dual damascene process

A system, method and program product for correcting a deviation of a dimension of a feature from a target in a semiconductor process, are disclosed. The invention determines an origin of a deviation in a feature dimension from a target dimension regardless of whether it is based on processing or metrology. Adjustments for wafer processing variation of previous process tools can be fed forward, and adjustments for the process and/or integrated metrology tools may be fed back automatically during the processing of semiconductor wafers. The invention implements process reference wafers to determine the origin in one mode, and measurement reference wafers to determine the origin of deviations in another mode.

Feature dimension deviation correction system, method and program product

The present invention, in one embodiment, provides a method of forming a gate structure including providing a substrate including a semiconducting device region, a high-k dielectric material present atop the semiconducting device region, and a metal gate conductor atop the high-k dielectric material, applying a photoresist layer atop the metal gate conductor; patterning the photoresist layer to provide an etch mask overlying a portion of the metal gate conductor corresponding to a gate stack; etching the metal gate conductor and the high-k dielectric material selective to the etch mask; and removing the etch mask with a substantially oxygen free nitrogen based plasma.

Nitrogen based plasma process for metal gate MOS device

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New Paltz, NY, United States of America

Wesley Charles Natzle