Infineon Technologies Ag

Infineon Technologies Austria Ag

Other

International Business Machines Corporation

Werner Robl

Jens G Pohl

Hans-Joachim Barth

Gottfried Beer

Rainer Steiner

Mathias Vaupel

Michael Nelhiebel

Stefan Woehlert

Thomas Goebel

Sven Lanzerstorfer

Joern Plagmann

Robert Illing

Hans-Joerg Timme

Klemens Pruegl

Bernhard Weidgans

Carsten Schaeffer

Evelyn Napetschnig

Roy Charles Iggulden

Axel Brintzinger

Michael Rogalli

Gerald R Friese

Tobias Schmidt

Thomas Detzel

Kamil Karlovsky

Paul Frank

Padraic C Shafer

Michael Ehmann

Eric Graetz

Frank Wagner

Gretchen Adema

Michael Fugger

Joachim Seifert

Maximilian Krug

Johann Gross

Thomas Bertaud

Manfred Engelhardt

Matthias Stecher

Kwong Hon Wong

Markus Brunnbauer

Guenther Ruhl

Manfred Schneegans

Thomas Fischer

Jay William Strane

Edmund Riedl

Rajeev Malik

Mihel Seitz

Markus Menath

Johannes Lodermeyer

Gerhard Poeppel

Peter Wrschka

Rainer Pelzer

Michael Melzl

Olaf Heitzsch

Jakob Kriz

Thomas Kunstmann

Andreas Zankl

Franziska Haering

Manfred Frank

Michael M Iwatake

Donna Diane Miura

Andreas Stueckjuergen

Juergen Foerster

Heiko Assmann

Ivan Nikitn

Joem Plagmann

Johannes Zechner

Kwong Hon (Keith) Wong

Chet Dziobkowski

An electronic device, an electronic module comprising the electronic device and methods for fabricating the same are disclosed. In one example, the electronic device includes a semiconductor substrate and a metal stack disposed on the semiconductor substrate, wherein the metal stack comprises a first layer, wherein the first layer comprises NiSi.

Electronic device, electronic module and methods for fabricating the same

A semiconductor device includes: a semiconductor substrate; a power device formed in the semiconductor substrate; a metal bilayer formed over the semiconductor substrate, the metal bilayer including a discontinuous metal layer formed on and in contact with a continuous base metal layer; and one or more contact pads formed in the metal bilayer or in a metallization layer above the metal bilayer. The discontinuous metal layer includes a plurality of metal blocks which are laterally spaced apart from one another and which form a heat sink structure over the power device. The continuous base metal layer is configured to laterally spread heat energy from the power device to the plurality of metal blocks. Methods of producing the semiconductor device are also described.

Semiconductor device power metallization layer with stress-relieving heat sink structure

According to various embodiments, a device may include: a semiconductor region; a metallization layer disposed over the semiconductor region; and a self-organizing barrier layer disposed between the metallization layer and the semiconductor region, wherein the self-organizing barrier layer comprises a first metal configured to be self-segregating from the metallization layer.

Semiconductor device and a method of forming the semiconductor device

An electrolyte may be provided. The electrolyte may include at least one additive configured to decompose or evaporate at a temperature above approximately 100&#xb0; C., and a water soluble metal salt, and the electrolyte may be free from carbon nanotubes. In various embodiments, a method of forming a metal layer may be provided: The method may include depositing a metal layer on a carrier using an electrolyte, wherein the electrolyte may include at least one additive configured to decompose or evaporate at a temperature above approximately 100&#xb0; C. and a water soluble metal salt, wherein the electrolyte is free from carbon nanotubes; and annealing the metal layer to form a metal layer comprising a plurality of pores. In various embodiments, a semiconductor device may be provided. The semiconductor device may include a metal layer including a plurality of pores, wherein the plurality of pores may be formed in the metal layer as remnants of an additive having resided in the plurality of pores and having at least partially decomposed or evaporated. To keep a high elasticity over a wide temperature range (up to 450&#xb0; C.), an adhesion layer may stabilize the metal grain boundaries and may fix dislocation gliding inside metal grains. In various embodiments, a metal layer is provided. The metal layer may include a plurality of pores having ellipsoidal or spheroidal shape.

Electrolyte, method of forming a copper layer and method of forming a chip

A semiconductor device includes a base element and a copper element over the base element. The copper element includes a layer stack having at least two copper layers and at least one intermediate conductive layer of a material different from copper. The at least two copper layers and the at least one intermediate conductive layer are alternately stacked over each other.

Semiconductor device having a copper element and method of forming a semiconductor device having a copper element

Self-organizing barrier layer disposed between a metallization layer and a semiconductor region

One or more embodiments relate to a method for making a semiconductor structure, comprising: providing a workpiece; forming a barrier layer over the workpiece; forming a separation layer over the barrier layer; forming a conductive layer over the separation layer; and wet etching the conductive layer.

Semiconductor structure and method for making same

An integrated circuit includes a base element and a copper element over the base element, the copper element having a thickness of at least 5 &#x3bc;m and a ratio of average grain size to thickness of less than 0.7.

Integrated circuit and method of forming an integrated circuit

One or more embodiments relate to a semiconductor structure, comprising: a barrier layer overlying a workpiece surface; a seed layer overlying the barrier layer; an inhibitor layer overlying said seed layer, the inhibitor layer having a opening exposing a portion of the seed layer, and a fill layer overlying the exposed portion of the seed layer.

One or more embodiments relate to a method of forming a semiconductor structure, comprising: providing a workpiece; forming a barrier layer over the workpiece; forming a seed layer over the barrier layer; forming an inhibitor layer over the seed layer; removing a portion of said inhibitor layer to expose a portion of the seed layer; and selectively depositing a fill layer on the exposed seed layer.

A semiconductor component has integrated a coreless transformer with a first connection contact, a second connection contact, an electrically conductive spiral first coil, an electrically conductive first ring, and an electrically conductive second ring. The electrically conductive spiral first coil is electrically connected between the first connection contact and the second connection contact. The electrically conductive first ring surrounds the first coil and one or both of the first connection contact and the second connection contact. The electrically conductive second ring is arranged between the first coil and the first ring, electrically connected to the first coil, and surrounds the first coil and one or both of the first connection contact and the second connection contact.

Semiconductor component with coreless transformer

According to various embodiments, a method for processing a semiconductor wafer or die is provided including supplying particles to a plasma such that the particles are activated by the plasma and spraying the activated particles on the semiconductor wafer or die to generate a particle layer on the semiconductor wafer or die.

Method for processing a semiconductor wafer or die, and particle deposition device

A method for fabricating a device includes providing a substrate including at least one contact and applying a dielectric layer over the substrate. The method includes applying a first seed layer over the dielectric layer, applying an inert layer over the seed layer, and structuring the inert layer, the first seed layer, and the dielectric layer to expose at least a portion of the contact. The method includes applying a second seed layer over exposed portions of the structured dielectric layer and the contact such that the second seed layer makes electrical contact with the structured first seed layer. The method includes electroplating a metal on the second seed layer.

Device fabricated using an electroplating process

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Wuppertal, Germany

Werner Robl