Shanghai Hua Hong Nec Electronics Company, Limited

Shanghai Huahong Grace Semiconductor Manufacturing Corporation

Shanghai Hua Hong Nec Electronics

Hua Hong Semiconductor (wuxi) Limited

Shanghai Hua Hong Electronics Co., Ltd.

Wensheng Qian

Donghua Liu

Jun Hu

Wenting Duan

Jing Shi

Tzuyin Chiu

Fan Chen

YungChieh Fan

TungYuan Chu

Haifang Zhang

Jiong Xu

Feng Han

Fei Wang

Shengan Xiao

Yukun Lv

Juanjuan Li

Zhengliang Zhou

Xiongbin Chen

Han Wang

Xiao Fan

Guanglong Chen

Ju Hu

Jialong Li

Ziquan Fang

Pengliang Ci

An image sensor and a method for forming the image sensor are provided. The method includes: providing a substrate; patterning the substrate to form a plurality of columnar structures configured in an array, wherein a first trench, a second trench, and a third trench are configured between adjacent columnar structures and respectively along a first direction, a second direction, and a third direction, side walls of the columnar structures perpendicular to the first direction are (110) crystal faces, and oblique sections of the columnar structures perpendicular to the third direction are (100) crystal faces; and forming a doped epitaxial layer in the first trench, the second trench and the cross trench. Therefore, for the image sensor, an upper part of the cross trench is improved with little defects after the cross trench is full filled, which can effectively reduce white pixels and thus improve the performance of the image sensor.

Image sensor and method for forming the same

The application discloses a method for making an LDMOS device and an LDMOS device, the method comprising steps of: forming a well doped region in a substrate; forming a gate oxide on the substrate; forming a polysilicon gate on the gate oxide, wherein the polysilicon gate and the gate oxide form a step structure; performing drift region ion implantation at least two times to form a drift region in the substrate, wherein the drift region covers the well doped region and the bottom of the gate oxide, and in the at least two times of drift region ion implantation, there is a difference in energy between at least two times of drift region ion implantation; and performing heavily doped ion implantation, to separately form a source terminal and a channel lead-out terminal in the well doped region and to form a drain terminal in the drift region.

Method for making LDMOS device and LDMOS device

Disclosed is an LDMOS device comprising a drift region formed by a selected area of a doped layer of a first conductivity type on a semiconductor substrate, a gate structure comprising a gate dielectric layer and a gate conductive layer which are sequentially formed on a surface of the doped layer of the first conductivity type, a doped self-aligned channel region of a second conductivity type, and a doped layer formed by tilted ion implantation with a first side face of the gate structure as a self-alignment condition. A method for manufacturing an LDMOS device is further disclosed. The channel length is not affected by lithography and thus can be minimized to fulfill an ultralow specific-on-resistance, and the distribution uniformity of the channel length can be improved, so that the performance uniformity of the device is improved.

LDMOS device and method for manufacturing same

The present invention discloses an LDMOS device, whose drift region is composed of a first drift region and a second drift region, the first drift region being composed of an ion implantation region formed in a selected region of the silicon substrate; the second drift region, composed of the doped polysilicon formed on the surface of the silicon substrate, is superimposed on the first drift region, with the drain region formed in the second drift region. With the second drift region of the present invention, the thickness of the entire drift region can be increased, and thus the parasitic resistance of the entire drift region can be reduced, the linear current of the device can be effectively increased, and the on-resistance of the device can be effectively reduced; the device of the present invention can also maintain a high breakdown voltage and lower process cost. The present invention further discloses a method for manufacturing the LDMOS device.

LDMOS device and its manufacturing method

An NLDMOS device that includes a drift region, a P well, and a first PTOP layer and a second PTOP layer formed on the drift region, wherein the first PTOP layer has the same lateral size with the second PTOP layer, the first PTOP layer is spaced from the second PTOP layer in the longitudinal direction and located on the bottom of the second PTOP layer, with the depth of the first PTOP layer less than or equal to that of the bottom of the P well. The present invention also discloses a method for manufacturing the NLDMOS device.

NLDMOS device and method for manufacturing the same

An isolation NLDMOS device including: an N well and a P well adjacent to each other on an upper part of a P substrate; on the upper part of the P well are sequentially arranged a first P type heavily doped region, a first field oxide, and a second P type heavily doped region; on the upper part of the N well are arranged a second field oxide and an N type heavily doped region; a gate oxide is between the second P type heavily doped region and the second field oxide; a gate polysilicon sits above the gate oxide and part of the second field oxide; from the first P type heavily doped region, the second P type heavily doped region and the N type heavily doped region are led out each a connecting wire via a respective contact hole.

Isolation NLDMOS device and a manufacturing method therefor

An LDMOS device is disclosed. The LDMOS device includes: a substrate having a first type of conductivity; a drift region having a second type of conductivity and a doped region having the first type of conductivity both formed in the substrate; a drain region having the second type of conductivity and being formed in the drift region, the drain region being located at an end of the drift region farther from the doped region; and a buried layer having the first type of conductivity and being formed in the drift region, the buried layer being in close proximity to the drain region and having a step-like bottom surface, and wherein a depth of the buried layer decreases progressively in a direction from the drain region to the doped region. A method of fabricating LDMOS device is also disclosed.

LDMOS device with step-like drift region and fabrication method thereof

A structure for picking up a collector region including a pair of polysilicon stacks formed in the isolation regions and extending below the collector region; and a pair of collector electrodes contacting on the polysilicon stacks, wherein the pair of polysilicon stacks includes: an undoped polysilicon layer and a doped polysilicon layer located on the undoped polysilicon layer, wherein a depth of the doped polysilicon layer is greater than a depth of the collector region; the depth of the collector region is greater than a depth of the isolation regions.

Structure for picking up a collector and method of manufacturing the same

An RF LDMOS device is disclosed, including: a substrate having a first conductivity type; a channel doped region having the first conductivity type and a drift region having a second conductivity type, each in an upper portion of the substrate, the channel doped region having a first end in lateral contact with a first end of the drift region; a first well having the first conductivity type in the substrate, the first well having a top portion in contact with both of a bottom of the first end of the channel doped region and a bottom of the first end of the drift region; and a second well having the first conductivity type in the substrate, the second well having a top portion in contact with a bottom of a second end of the drift region. A method of forming such an RF LDMOS device is also disclosed.

RF LDMOS device and method of forming the same

A radio frequency (RF) laterally diffused metal oxide semiconductor (LDMOS) device is disclosed, wherein a lightly doped n-type drain region has a laterally non-uniform n-type dopant concentration distribution, which is achieved by forming a moderately n-type doped region, having a higher doping concentration and a greater depth than the rest portion of the lightly doped n-type drain region, in a portion of the lightly n-type doped region proximate to the polysilicon gate. The structure enables the RF LDMOS device of the present invention to have both a high breakdown voltage and a significantly reduced on-resistance. A method of fabricating such a RF LDMOS device is also disclosed.

RF LDMOS device and fabrication method thereof

An LDMOS device is disclosed. The LDMOS device includes: a substrate having a first type of conductivity; a drift region having a second type of conductivity and being formed in the substrate; a doped region having the first type of conductivity and being formed in the substrate, the doped region being located at a first end of the drift region and laterally adjacent to the drift region; and a heavily doped drain region having the second type of conductivity and being formed in the substrate, the heavily doped drain region being located at a second end of the drift region, wherein the drift region has a step-like top surface with at least two step portions, and wherein a height of the at least two step portions decreases progressively in a direction from the doped region to the drain region. A method of fabricating LDMOS device is also disclosed.

A SiGe HBT is disclosed, which includes: a silicon substrate; shallow trench field oxides formed in the silicon substrate; a pseudo buried layer formed at bottom of each shallow trench field oxide; a collector region formed beneath the surface of the silicon substrate, the collector region being sandwiched between the shallow trench field oxides and between the pseudo buried layers; a polysilicon gate formed above each shallow trench field oxide having a thickness of greater than 150 nm; a base region on the polysilicon gates and the collector region; emitter region isolation oxides on the base region; and an emitter region on the emitter region isolation oxides and a part of the base region. The polysilicon gate is formed by gate polysilicon process of a MOSFET in a CMOS process. A method of manufacturing the SiGe HBT is also disclosed.

SiGe HBT and method of manufacturing the same

A silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) is disclosed, including: a substrate; two field oxide regions formed in the substrate; two pseudo buried layers, each being formed under a corresponding one of the field oxide regions; a collector region formed between the field oxide regions, the collector region laterally extending under a corresponding one of the field oxide regions and each side of the collector region being connected with a corresponding one of the pseudo buried layers; a matching layer formed under both the pseudo buried layers and the collector region; and two deep hole electrodes, each being formed in a corresponding one of the field oxide regions, the deep hole electrodes being connected to the corresponding ones of the pseudo buried layers for picking up the collector region. A manufacturing method of the SiGe HBT is also disclosed.

Silicon-germanium heterojunction bipolar transistor and manufacturing method thereof

A zener diode in a SiGe BiCMOS process is disclosed. An N-type region of the zener diode is formed in an active region and surrounded by an N-deep well. A pseudo buried layer is formed under each of the shallow trench field oxide regions on a corresponding side of the active region, and the N-type region is connected to the pseudo buried layers via the N-deep well. The N-type region has its electrode picked up by deep hole contacts. A P-type region of the zener diode is formed of a P-type ion implanted region in the active region. The P-type region is situated above and in contact with the N-type region, and has a doping concentration greater than that of the N-type region. The P-type region has its electrode picked up by metal contact. A method of fabricating zener diode in a SiGe BiCMOS process is also disclosed.

Zener diode in a SiGe BiCMOS process and method of fabricating the same

A silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) having a deep pseudo buried layer is disclosed. The SiGe HBT includes isolation structures formed in trenches, first pseudo buried layers and second pseudo buried layers, and a collector region. The first pseudo buried layers are formed under the respective trenches and the second pseudo buried layers are formed under the first pseudo buried layers, with each first pseudo buried layer vertically contacting with a second pseudo buried layer. The second pseudo buried layers are laterally connected to each other, and the collector region is surrounded by the trenches, the first pseudo buried layers and the second pseudo buried layers. The cross section of each of the trenches has a regular trapezoidal shape, namely, each trench's width of its top is smaller than that of its bottom. A manufacturing method of the SiGe HBT is also disclosed.

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Shanghai, China

Wensheng Qian