Globalfoundries Inc.

Applied Materials, Inc.

Oplink Communications, Inc.

International Business Machines Corporation

Stmicroelectronics Gmbh

Varian Semiconductor Equipment Associates, Inc.

Wenhui Wang

Lei Sun

Huixiong Dai

Christopher S Ngai

Ryan Ryoung-Han Kim

Jia Zeng

Jason Cantone

Ruilong Xie

Jongwook Kye

Xuelian Zhu

Yulu Chen

Erik A Verduijn

Min Gyu Sung

Yann Mignot

Hosadurga K Shobha

Chi-Chun Liu

Feng Quan Liu

Terry Allen Spooner

Yan E Wang

Mahendra Pakala

Yongan Xu

Cheng Chi

Chando Park

Shyng-Tsong Chen

Vimal Kumar Kamineni

Lei Yuan

Chentsau Chris Ying

Nicholas V Licausi

Sahil Patel

Lin Xue

Jaesoo Ahn

Jong Mun Kim

Linus Jang

Abner Bello

Minrui Yu

Michael Wedlake

Seowoo Nam

Sylvie M Mignot

Wei Zhong Li

Chenchen Wang

Hui Zang

Chanro Park

Xunyuan Zhang

Xianmin Tang

Guillaume Bouche

Shifang Li

Azat M Latypov

Hao Chen

Guoxiang Ning

Sony Varghese

Joung Joo Lee

Bencherki Mebarki

Keith Tatseun Wong

Tamer Coskun

Wei-Zhong Li

Daniel James Dechene

Youngtag Woo

Liqi Wu

Mark Shi Wang

Shao Beng Law

Zhimin Liu

Yongmei Chen

Wei Luo

Wenyu Zhang

Jun Seok Lee

Zhengqing John Qi

Ke Chang

Yanbin Shao

Ryan Kim

Methods of forming and processing semiconductor devices which utilize a three-color hardmask process are described. Certain embodiments relate to the formation of self-aligned contacts for metal gate applications. More particularly, certain embodiments relate to the formation of self-aligned gate contacts through the selective deposition of a fill material.

Contact over active gate structure

Embodiments of the present disclosure generally include spin-orbit torque magnetoresistive random-access memory (SOT-MRAM) devices and methods of manufacture thereof. The SOT-MRAM devices described herein include an SOT layer laterally aligned with a magnetic tunnel junction (MTJ) stack and formed over a trench in an interconnect. Thus, the presence of the SOT layer outside the area of the MTJ stack is eliminated, and electric current passes from the interconnect to the SOT layer by SOT-interconnect overlap. The devices and methods described herein reduce the formation of shunting current and enable the MTJ to self-align with the SOT layer in a single etching process.

Spin-orbit torque MRAM structure and manufacture thereof

Implementations of the present disclosure generally relate to the fabrication of integrated circuits, and more particularly, to methods for forming a layer. The layer may be a mask used in lithography process to pattern and form a trench. The mask is formed over a substrate having at least two distinct materials by a selective deposition process. The edges of the mask are disposed on an intermediate layer formed on at least one of the two distinct materials. The method includes removing the intermediate layer to form a gap between edges of the mask and the substrate and filling the gap with a different material than the mask or with the same material as the mask. By filling the gap with the same or different material as the mask, electrical paths are improved.

Method for forming a layer

Methods of forming and processing semiconductor devices which utilize a three-color hardmask process are described. Certain embodiments relate to the formation of self-aligned contacts for metal gate applications. More particularly, certain embodiments relate to the formation of self-aligned gate contacts utilizing selective deposition of masks in a three-color process.

Methods of forming and processing semiconductor devices which utilize a three-color process are described. Certain embodiments relate to the formation of self-aligned contacts for metal gate applications. More particularly, certain embodiments relate to the formation of self-aligned gate contacts utilizing selective deposition of overlapping masks in a three-color process.

Methods and apparatus for processing a substrate are provided herein. In some embodiments, a method for processing a substrate includes: directing a stream of material from a PVD source toward a surface of a substrate at a first non-perpendicular angle to the plane of the surface to deposit the material on one or more features on the substrate and form a first overhang; etching the layer of the substrate beneath the features selective to the deposited material to form a first part of a pattern; removing the material from the features; directing the stream of material from the PVD source toward the surface of the substrate at a second non-perpendicular angle to the plane of the surface to deposit the material on the features on the substrate and form a second overhang; and etching the layer of the substrate beneath the features selective to the deposited material to form a second part of the pattern.

Methods and apparatus for patterning substrates using asymmetric physical vapor deposition

A method may include providing a device structure, where the device structure includes a semiconductor region, and a gate structure, disposed over the semiconductor region. The gate structure may further include a gate metal. The method may further include oxidizing an upper portion of the gate metal, wherein the upper portion forms an oxide cap, and wherein a lower portion of the gate metal remains metallic.

Techniques for contact formation in self-aligned replacement gate device

The disclosure relates to integrated circuit (IC) structures with substantially T-shaped wires, and methods of forming the same. An IC structure according to the present disclosure can include a first substantially T-shaped wire including a first portion extending in a first direction, and a second portion extending in a second direction substantially perpendicular to the first direction; an insulator laterally abutting the first substantially T-shaped wire at an end of the first portion, opposite the second portion; and a pair of gates each extending in the first direction and laterally abutting opposing sidewalls of the insulator and the first portion of the substantially T-shaped wire.

Integrated circuit structure including power rail and tapping wire with method of forming same

Methods of forming printed patterns and structures formed using printed patterns. A first line and a second line are lithographically printed in a first layer composed of photoimageable material with a space arranged between the first line and the second line. A dummy assist feature is also lithographically printed in the photoimageable material of the first layer. A second layer underlying the first layer is etched with the first line, the second line, and the dummy assist feature present as an etch mask. The dummy assist feature is arranged on a portion of the space adjacent to the first line and supports the photoimageable material of the first line during etching.

Dummy assist features for pattern support

Process of using a dummy gate as an interconnection and a method of manufacturing the same are disclosed. Embodiments include forming on a semiconductor substrate dummy gate structures at cell boundaries, each dummy gate structure including a set of sidewall spacers and a cap disposed between the sidewall spacers; removing a first sidewall spacer or at least a portion of a first cap on a first side of a first dummy gate structure and forming a first gate contact trench over the first dummy gate structure; and filling the first gate contact trench with a metal to form a first gate contact.

Dummy gate used as interconnection and method of making the same

The present disclosure relates to semiconductor structures and, more particularly, to contacts for local connections and methods of manufacture. The structure includes: at least one contact electrically shorted to a gate structure and a source/drain contact and located below a first wiring layer; and gate, source and drain contacts extending from selected gate structures and electrically connecting to the first wiring layer.

Structure with local contact for shorting a gate electrode to a source/drain region

A method of forming a via to an underlying layer of a semiconductor device is provided. The method may include forming a pillar over the underlying layer using a sidewall image transfer process. A dielectric layer is formed over the pillar and the underlying layer; and a via mask patterned over the dielectric layer, the via mask having a mask opening at least partially overlapping the pillar. A via opening is etched in the dielectric layer using the via mask, the mask opening defining a first lateral dimension of the via opening in a first direction and the pillar defining a second lateral dimension of the via opening in a second direction different than the first direction. The via opening is filled with a conductor to form the via. A semiconductor device and via structure are also provided.

Via formation using sidewall image transfer process to define lateral dimension

Methods for fabricating integrated circuits are provided. In one example, a method includes providing a circuit structure layer over a substrate and at least one etch layer over the circuit structure layer, in the at least one etch layer patterning at least one primary pattern feature having at least one primary pattern feature dimension and at least one assist pattern feature having at least one assist pattern feature dimension, where the primary pattern feature dimension is greater than the assist pattern feature dimension, reducing the at least one primary pattern feature dimension and closing the assist pattern feature to form an etch pattern, and etching a circuit structure feature using the etch pattern.

Shrink process aware assist features

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San Jose, CA, United States of America

Wenhui Wang