Advanced Micro Devices Corporation

Other

Tokyo Electron Limited

Spansion Llc.

Timbre Technologies, Inc.

Wenge Yang

Lewis N Shen

Fei Wang

Ramkumar Subramanian

Kashmir S Sahota

Minh Van Ngo

Hiroyuki Kinoshita

YongZhong Hu

Yu Nan Sun

Bhanwar Singh

Mark T Ramsbey

Angela Tai Hui

Suzette Keefe Pangrle

John JianShi Wang

Bharath Rangarajan

Junwei Bao

Marina V Plat

Mark S Chang

Hao Fang

Nickhil Jakatdar

Xinhui Niu

Yasuhiro Okumoto

Alan Nolet

Bhanwar Sinjh

In semiconductor processing, the critical dimensions of structures formed on a wafer are controlled by first developing photoresist on top of a film layer on a wafer using a developer tool, the photoresist development being a function of developer tool process variables including temperature and length of time of development. After developing the photoresist, one or more etching steps are performed on the film layer on the wafer using an etch tool. After the one or more etching steps are performed, critical dimensions of structures at a plurality of locations on the wafer are measured using an optical metrology tool. After the critical dimensions are measured, one or more of the developer tool process variables are adjusted based on the critical dimensions of structures measured at the plurality of locations on the wafer.

Controlling critical dimensions of structures formed on a wafer in semiconductor processing

A process for making semiconductor structures uses a decoupled plasma source to produce a highly selective plasma etchant to form a structure with a thin adhesive layer and overlaying conductive layer. The preferred plasma is formed from chlorine and oxygen feed gases. The highly conductive semiconductor structure has a thickness less than about 3000 &#x212b;, preferably less than about 2600 &#x212b;, and incorporates an adhesive layer that is preferably less than about 100 &#x212b; thick. Despite the reduced profile and topography of the structure, it is more conductive than prior structures, and provides a robust device.

Method of forming highly conductive semiconductor structures via plasma etch

A method is provided for manufacturing a semiconductor device on a semiconductor substrate using a dielectric as a bottom anti-reflective coating for formation of a photoresist contact opening which is used to enlarge the Final Inspection Critical Dimension (FICD) of the conductive contact. A high selectivity etch is used to form a tapered contact.

Method for forming SAC using a dielectric as a BARC and FICD enlarger

A metrology method and system of structures on a wafer includes obtaining a projection image of at least a first portion of the structures on the wafer using a first metrology apparatus. A profile of at least a second portion of the structure on the wafer is obtained using a second metrology apparatus. The information from the profile obtained using the second metrology apparatus and the information from the projection image obtained using the first metrology apparatus are combined using a processor.

Combined optical profilometry and projection microscopy of integrated circuit structures

A process for making semiconductor structures, and the resulting highly conductive semiconductor structures, includes using damascene process to form a structure with a thin adhesive layer and overlaying conductive layer. The highly conductive semiconductor structure has a thickness less than about 3000 &angst;, preferably less than about 2600 &angst;, and incorporates an adhesive layer that is preferably less than about 100 &angst; thick. Despite the reduced profile and topography of the structure, it is more conductive than prior structures, and provides a robust device.

Method for fabricating a conductive structure for a semiconductor device

The present invention relates to a methodology of fabricating a local interconnect. The methodology includes the steps of forming an organic stop layer over a semiconductor structure having at least one conductive region, forming an insulating layer over the organic layer, forming a photoresist layer over the insulating layer, patterning the photoresist layer with at least one opening above the at least one conductive region, etching at least one opening in the insulating layer, concurrently stripping the photoresist layer and an exposed portion of the organic layer and filling the at least one opening with a conductive material to form the local interconnect.

Use of organic spin on materials as a stop-layer for local interconnect, contact and via layers

The high density plasma metal etch rate of a conductive material within a dense array of conductive lines is increased to greater than the etch rate of the conductive material in a bordering open field by controlling the source power and the bottom power in a plasma chamber, thereby reducing overetching, resist loss, and oxide loss in the open field, and facilitating planarization.

Method of high density plasma metal etching

The use of chlorine and oxygen chemistry in a polysilicon etch environment provides a process to etch a plurality of silicon-based layers on a semiconductor substrate to an underlying oxide layer in a single step. The process is useful in the formation of gate structures wherein high selectivity to the underlying oxide layer thereby affords higher processing control over the formed gate structure.

Semiconductor devices with reduced control gate dimensions

A method of manufacturing a semiconductor device is provided in which multi-layer structures are formed on a semiconductor substrate to form core and peripheral regions. Sidewall spacers are formed around the multi-layer structures and source and drain regions are implanted adjacent the sidewall spacers and a stop layer is deposited over the semiconductor substrate after which a dielectric layer is deposited over the stop layer. A first and second photoresist contact masks are deposited, processed, and used to respectively etch core and peripheral contact openings. The first and photoresist contact masks are respectively removed after each etching step. A conductive material is deposited over the dielectric layer and in the core and peripheral contact openings and is chemical mechanical planarized to remove the conductive material over the dielectric layer so the conductive material is left isolated in the core and peripheral contact openings with core contacts to the source/drain regions and peripheral contacts to the local interconnect gate contacts of the multi-layer structures and the source/drain regions.

Method for forming self-aligned contacts and local interconnects using decoupled local interconnect process

A resist mask pattern having a reduced thickness is formed overlying on a silicon oxynitride film during formation of a memory gate. The resist mask pattern has a resist thickness (3000 to 4000 Angstroms) sufficient to withstand removal during etching of the silicon oxynitride film. The silicon oxynitride film, having a thickness of about 800 to 1500 Angstroms, is etched based on the resist mask pattern and then used as a mask pattern to etch the polysilicon gate layer underlying the silicon oxynitride layer, to expose a portion of an isolation region aligned relative to the resist mask pattern. The portion of the resist mask remaining after etching, in combination with the etched silicon oxynitride film, have a sufficient overall thickness to serve as a channel implant mask. Use of the resist mask pattern having the reduced thickness improves yield by minimizing the occurrence of misregistration, and enables reliable formation of spaces in the mask pattern having widths of less than 0.25 microns using conventional deep ultraviolet (DUV) photolithography techniques.

Method and structure of etching a memory cell polysilicon gate layer using resist mask and etched silicon oxynitride

A shallow trench isolation (STI) region is covered with a nitride layer. The nitride layer, advantageously, fills in gaps in the underlying dielectric layer, such as seams, thereby reducing leakage. The nitride layer may be patterned to form a spacer above the STI region which is used to define an opening in the polysilicon layer that is subsequently deposited. The polysilicon layer is etched back to expose the nitride spacer, which is then etched away in a controlled fashion. Thus, a small opening may be formed in the polysilicon layer. Further, because the polysilicon layer is etched back to the top of the nitride spacer, the polysilicon layer is planarized thereby reducing stringers in subsequent processing.

Method of fabricating a shallow trench isolation structure with reduced topography

In one embodiment, a process for reducing the step height of shallow trench isolation structures includes the acts of (a) forming a hard mask on a semiconductor substrate to define a trench, (b) forming the trench, (c) filling the trench with a dielectric material, (d) planarizing the dielectric material,(e) replacing the hard mask with a resist mask, (f) etching back the dielectric material to reduce its step height, and (g) removing the resist mask. In another embodiment, the hard mask used to define the trench is used during the etch back of the dielectric material. In another embodiment, the hard mask used to define the trench is partially stripped before the dielectric material is planarized to reduce its step height.

Method for reducing the step height of shallow trench isolation structures

The present invention relates to a method for forming an etch mask. A photoresist layer is patterned, wherein d is a smallest space dimension of an exposed area of a layer underlying the photoresist layer. A polymer layer is formed to be conformal to the patterned photoresist layer and exposed portions of the underlayer. The polymer layer is etched to form polymer sidewalls, the polymer sidewalls reducing the smallest space dimension of the exposed underlayer area to d , wherein d <d .

Method to produce small space pattern using plasma polymerization layer

A memory gate stack in a high density memory core has spaces on the order of less than 0.25 microns using conventional deep ultraviolet (DUV) lithography techniques by depositing a layer of silicon oxynitride over a plurality of layers, and a thin resist layer overlying on the silicon oxynitride layer. The resist layer has a thickness sufficient to withstand removal during etching of the silicon oxynitride layer, for example about 3,000 Angstroms to about 4,000 Angstroms. The silicon oxynitride layer has a sacrificial portion having a thickness at least about 500 Angstroms, and a stop-layer thickness, used for spacer formation following etching of the memory gate, of at least 1,000 Angstroms. The use of silicon oxynitride as an antireflective coating layer in combination with the thin resist optimizes the resolution of DUV lithography, enabling formation of spacers having widths less than about 0.24 microns. In addition, the sacrificial layer of the silicon oxynitride layer enables self-aligned etching of the plurality of layers to form the memory gate stack, while maintaining sufficient thickness for spacer formation.

Method for etching memory gate stack using thin resist layer

The present invention provides a method for manufacturing a semiconductor device without the use of an anti-reflective coating. In one embodiment, electrical devices are formed on a semiconductor substrate. A material with a low dielectric constant such as an oxide is then deposited. The low dielectric layer is then covered with photoresist and photolithographically processed and subsequently developed. The low dielectric layer is then etched using the pattern formed on the photoresist and the photoresist is later removed. Because this process works in any similar circumstances, good examples of its application are the formation of both contacts and local interconnects.

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Fremont, CA, United States of America

Wenge Yang