Macronix International Co., Ltd.

Weng-Hsing Huang

Kent Kuohua Chang

Chen-Chin Liu

Chin-Yi Huang

A memory device and a method for fabricating the same are described. The memory device includes a substrate, buried bit lines, word line structures, a dielectric layer, conductive lines in trenches and self-aligned contacts. The buried bit lines are located in the substrate, and the word line structures are disposed on the substrate crossing over the buried bit lines. Each word line structure consists of a word line, a gate oxide layer, a capping layer and a spacer. Each conductive line is disposed in the dielectric layer and over a buried bit line, and crosses over the capping layers. The dielectric layer is disposed between the word line structures and between the conductive lines. Each self-aligned contact is disposed under a conductive line and between two adjacent word lines to electrically connect the conductive line and the corresponding buried bit line.

Memory device and method for fabricating the same

The present invention provides a memory structure, comprising: a substrate; a gate oxide layer disposed on a portion of the substrate; a gate structure disposed on the gate oxide layer; a buried bit line disposed in the substrate along both sides of the gate structures; a raised line disposed on the burled bit line; an isolating spacer disposed on both sidewalls of the gate structure and a word line disposed over the substrate in a direction perpendicular to the buried bit line; and an insulation layer disposed on a top of the raised line to electrically isolate the raised line and the word line.

Memory device structure with composite buried and raised bit line

A method for reducing random bit failures of flash memory fabrication processes with an HTO film. The random bit failures are caused by HF acid penetration. The HTO film, which functions as an interface reinforcement layer, is formed on a sacrificial layer and a PL layer. With the aid of the HTO film, the flash memory is free of acid-corroded seams.

Method for improving the reliability of flash memories

Memory device with low resistance buried bit lines

A semiconductor wafer includes a substrate, a polysilicon layer, and a sacrificial layer on the polysilicon layer. A dielectric layer is formed to cover the substrate and the sacrificial layer. A portion of the dielectric layer is removed to expose an upper portion of the sidewalls of the sacrificial layer. A passivation layer is formed on the surface of the dielectric layer and contacts the exposed sidewalls of the sacrificial layer. The passivation layer and the dielectric layer positioned over the sacrificial layer are removed down to a predetermined height by CMP. The dielectric layer is removed from the sacrificial layer, followed by removing the passivation layer and removing the sacrificial layer. A recess is thus formed with the polysilicon layer as the bottom of the recess and the remaining dielectric layer as the walls. Finally, another polysilicon layer is formed on the semiconductor wafer to form a floating gate.

Growing community of inventors

Hsinchu, Taiwan

Weng-Hsing Huang