Freescale Semiconductor,inc.

Nxp Usa, Inc.

Nsp Usa, Inc.

Weng Foong Yap

Michael B Vincent

Zhiwei Gong

Alan J Magnus

Jason R Wright

Eduard Jan Pabst

Scott M Hayes

Jinbang Tang

Douglas G Mitchell

Boh Kid Wong

Lai Cheng Law

Trung Duong

Sandeep Shantaram

Kesvakumar V C Muniandy

Sergio P Pacheco

Fui Yee Lim

Dominic Koey Poh Meng

Embodiments of a packaged electronic device and method of fabricating such a device are provided, where the packaged electronic device includes: a pressure sensor die having a diaphragm on a front side; an encapsulant material that encapsulates the pressure sensor die, wherein the front side of the pressure sensor die is exposed at a first major surface of the encapsulant material; an interconnect structure formed over the front side of the pressure sensor die and the first major surface of the encapsulant material, wherein an opening through the interconnect structure is generally aligned to the diaphragm; and a cap attached to an outer dielectric layer of the interconnect structure, the cap having a vent hole generally aligned with the opening through the interconnect structure.

Packaged pressure sensor device

Embodiments are provided for a packaged semiconductor device that includes a package substrate that in turn includes an embedded die configured to process a radio frequency (RF) signal; a printed circuit board (PCB) attached to a front side of the package substrate, where the PCB includes a cavity; and an antenna enabling element attached to the front side of the package substrate within the cavity, the antenna enabling element configured to convey the RF signal through the cavity.

Antenna assembly for wafer level packaging

Microelectronic packages and methods for fabricating microelectronic packages having optical mask layers are provided. In one embodiment, the method includes building redistribution layers over the frontside of a semiconductor die. The redistribution layers includes a body of dielectric material in which a plurality of interconnect lines are formed. An optical mask layer is formed over the frontside of the semiconductor die and at least a portion of the redistribution layers. The optical mask layer has an opacity greater than the opacity of the body of dielectric material and blocks or obscures visual observation of an interior portion of the microelectronic package through the redistribution layers.

Optically-masked microelectronic packages and methods for the fabrication thereof

A semiconductor device package and method of manufacturing is provided. An interconnect pre-assembly includes a first frame having a plurality of first signal conduits affixed to a second frame having a plurality of second signal conduits embedded in a second substrate forming an electrical coupling between one or more first signal conduits and one or more of the second signal conduits. One or more conductive balls are connected to the one or more second signal conduits. The interconnect pre-assembly is placed over a semiconductor die, having at least one of the first conductive balls disposed over the semiconductor die. An encapsulant encapsulates the interconnect pre-assembly, the semiconductor die, and the one or more conductive balls, such that a portion of the one or more first conductive balls is exposed at a top surface of the encapsulant.

Semiconductor device package and methods of manufacture thereof

Methods for producing System-in-Packages (SiPs) containing embedded Surface Mount Device (SMD) modules are provided, as SiPs containing SMD modules. In one embodiment, the fabrication method includes positioning a semiconductor die and first preassembled SMD module, which contains a plurality of SMDs soldered to an interposer substrate, in predetermined spatial relationship. The preassembled SMD module and the semiconductor die are overmolded to yield a molded panel having a frontside at which the first preassembled SMD module and the semiconductor die are exposed. A Redistribution Layer (RDL) structure can be formed over the frontside of the molded panel containing interconnect lines electrically coupling the semiconductor die and the first preassembled SMD module. The molded panel may then undergo singulation to produce an SiP having a molded body in which the semiconductor die and the first preassembled SMD module are embedded.

System-in-packages containing preassembled surface mount device modules and methods for the production thereof

Embodiments of a method for fabricating System-in-Packages (SiPs) are provided, as are embodiments of a SiP. In one embodiment, the method includes producing a first package including a first molded package body having a sidewall. A first leadframe is embedded within the first molded package body and having a first leadframe lead exposed through the sidewall. In certain implementations, a semiconductor die may also be encapsulated within the first molded package body. A Surface Mount Device (SMD) is mounted to the sidewall of the first molded package body such that a first terminal of the SMD is in ohmic contact with the first leadframe lead exposed through the sidewall.

Leadframe-based system-in-packages having sidewall-mounted surface mount devices and methods for the production thereof

A wafer level packaging method entails providing electronic devices and providing a platform structure having cavities extending through the platform structure. The platform structure is mounted to a temporary support. One or more electronic devices are placed in the cavities with an active side of each electronic device facing the temporary support. The platform structure and the electronic devices are encapsulated in an encapsulation material to produce a panel assembly. Redistribution layers may be formed over the panel assembly, after which the panel assembly may be separated into a plurality of integrated electronic packages. The platform structure may be formed from a semiconductor material, and platform segments within each package provide a fan-out region for conductive interconnects, as well as provide a platform for a metallization layer and/or for forming through silicon vias.

Integrated electronic package and stacked assembly thereof

Fan-Out Wafer Level Packages (FO-WLPs) and methods for fabricating FO-WLPs containing Embedded Ground Planes (EGPs) and backside EGP interconnect structures are provided. In one embodiment, the method includes electrically coupling an EGP to a backside terminal of a first microelectronic device through a backside EGP interconnect structure. A molded package body is formed around the first microelectronic device, the EGP, and the EGP interconnect structure. The molded package body has a frontside at which the EGP is exposed. One or more Redistribution Layers are formed over the frontside of the molded packaged body and contain at least one interconnect line electrically coupled to the backside contact through the EGP and the backside EGP interconnect structure.

Fan-out wafer level packages containing embedded ground plane interconnect structures and methods for the fabrication thereof

Stacked microelectronic package assemblies are provided, as are methods for producing stacked microelectronic package assemblies. In one embodiment, the stacked microelectronic package assembly includes a base package layer onto which a stacked bridge device is stacked. The base package layer includes, in turn, a first microelectronic package and a second microelectronic package positioned laterally adjacent the first microelectronic package. The stacked bridge device extends over the first and second microelectronic packages. A first terminal of the stacked bridge device is soldered to or otherwise electrically joined to a first backside contact of the first microelectronic package, and a second terminal of the stacked bridge device is soldered to or otherwise electrically joined to a second backside contact of the second microelectronic package.

Stacked microelectronic package assemblies and methods for the fabrication thereof

Radio frequency/electromagnetic interference (RF/EMI) shielding within redistribution layers of a fan-out wafer level package is provided. By using RDL metal layers to provide the shielding, additional process steps are avoided (e.g., incorporating a shielding lid or applying conformal paint on the package back side). Embodiments use metal filled trench vias in the RDL dielectric layers to provide metal 'walls' around the RF sensitive signal lines through the dielectric layer regions of the RDL. These walls are coupled to ground, which isolates the signal lines from interference or noise generated outside the walls.

Radio frequency and electromagnetic interference shielding in wafer level packaging using redistribution layers

A method for fabricating a stacked microelectronic device includes attaching a first package layer to a second package layer to form stacked microelectronic layers. Saw streets of the first package layer overlie and are aligned with saw streets of the second package layer. The first and second package layers include respective edge connectors formed between the saw streets and electronic components in the first and second package layers. A through package via is formed in one of the saw streets of the first and second package layers. The via is filled with conductive material. The stacked package layers are singulated along the saw streets in a manner that retains a portion of the conductive material to form a sidewall connector between at least two of the edge connectors.

Stacked microelectronic packages having sidewall conductors and methods for the fabrication thereof

Wafer level packages and methods for producing wafer level packages having delamination-resistant redistribution layers are provided. In one embodiment, the method includes building inner redistribution layers over a semiconductor die. Inner redistribution layers include a body of dielectric material containing metal routing features. A routing-free dielectric block is formed in the body of dielectric material and is uninterrupted by the metal routing features. An outer redistribution layer is produced over the inner redistribution layers and contains a metal plane, which is patterned to include one or more outgassing openings overlying the routing-free dielectric block. The routing-free dielectric block has a minimum width, length, and depth each at least twice the thickness of the outer redistribution layer.

Wafer level packages and methods for producing wafer level packages having delamination-resistant redistribution layers

An integrated electronic package includes an integrated circuit (IC) die and conductive discrete components. Electrical interconnects are formed directly between bond pads on an active side of the IC die and contacts on the conductive discrete components without an intervening lead frame. The IC die, conductive discrete components and electrical interconnects are embedded in an encapsulation material. Contact surfaces of at least some of the conductive discrete components are exposed from the encapsulation material and can be attached to a printed circuit board in order to mount the integrated electronic package to the printed circuit board.

Integrated electronic package and method of fabrication

Wafer level packages and methods for producing wafer level packages having non-wettable solder collars are provided. In one embodiment, the method includes forming solder mask openings in a solder mask layer exposing regions of a patterned metal level underlying the solder mask layer. Before or after forming solder mask openings in the solder mask layer, non-wettable solder collars are produced extending partially over the exposed regions of the patterned metal level. Solder balls are deposited onto the non-wettable solder collars and into the solder mask openings such that circumferential clearances are provided around base portions of the solder balls and sidewalls of the solder mask layer defining the solder mask openings.

Growing community of inventors

Chandler, AZ, United States of America

Weng Foong Yap