Etron Technology, Inc.

Other

Invention and Collaboration Laboratory Pte. Ltd.

Weng-Dah Ken

Chao-Chun Lu

Jan-Mye Sung

Nicky C Lu

Bor-Doou Rong

Fang-Chi Kan

A method for filtering matter waves (MW) from a composite particle beam, comprising: obtaining the composite particle beam from a first particle path, the beam comprising a matter-wave-energy (an MWE) particle component and a matter wave (an MW) component, wherein the MW component does not correspond to the MWE particle component; directing the composite particle beam toward a unit having a distribution of a non-uniform spatial field; tilting the MWE particle component of the composite particle beam toward a second path away from the first path; generating an output beam of the MW component along the first path going through the non-uniform spatial field; and receiving the output beam of the MW component for processing in a subsequent step.

Ultra-precision timing clock method

A transistor with low leakage currents includes a substrate, a gate, spacers, pad dielectric layers, a source, and a drain. The gate is formed above a gate dielectric layer, wherein the gate dielectric layer has a first dielectric constant. The spacers have a second dielectric constant. The pad dielectric layers are formed under the spacers and having a third dielectric constant. The source and the drain are adjacent to the spacers and in two opposite directions of the gate. The first dielectric constant, the second dielectric constant, and the third dielectric constant are different from each other.

Transistor with low leakage currents and manufacturing method thereof

A non-contact angle measuring apparatus includes a matter-wave and energy (MWE) particle source and a detector. The MWE particle source is used for generating boson or fermion particles. The detector is used for detecting a plurality peaks or valleys of an interference pattern generated by 1) the boson or fermion particles corresponding to a slit, a bump, or a hole of a first plane and 2) matter waves' wavefront-split associated with the boson or fermion particles reflected by a second plane, wherein angular locations of the plurality peaks or valleys of the interference pattern, a first distance between a joint region of the first plane and the second plane, and a second distance between the detector and the slit are used for deciding an angle between the first plane and the second plane.

Non-contact angle measuring apparatus

A green bike comprises a frame, two wheels, a first internal-gear module and a second internal-gear module and a transmission element. The frame has a pedal, a front supporting unit, a rear supporting unit, and a seat unit. The two wheels are attached to the front supporting unit and the rear supporting unit, respectively. The transmission element is disposed in the frame or a tube shield linking to the frame. The first internal-gear module and the second internal-gear module are coupled with the pedal and at least one of the wheels. The transmission element links the first and the second internal-gear modules for delivering power to the at least one of the wheels.

Green bike

A system-in-package module with memory includes a non-memory chip, a substrate, and a memory chip. The non-memory chip has a first portion and a second portion. The substrate has a window and the substrate is electrically connected to the second portion of the non-memory chip. The memory chip is placed into the window of the substrate to electrically connect the first portion of the non-memory chip, and there is no direct metal connection between the memory chip and the substrate.

System-in-package module with memory

A reconfigurable high speed memory chip module includes a type of memory cell array group, a first transmission bus, and a logic unit. The type memory cell array group includes multiple memory cell array integrated circuits (ICs). The first transmission bus coupled to the type memory cell array group has a first programmable transmitting or receiving data rate, a first programmable transmitting or receiving signal swing, a first programmable bus width, and a combination thereof. The logic unit is coupled to the first transmission bus for accessing the type memory cell array group through the first transmission bus.

Reconfigurable high speed memory chip module and electronic device with a reconfigurable high speed memory chip module

A system-in-package module includes a non-memory chip, a bundled memory, and an encapsulation package material. The non-memory chip has a plurality of pads. The bundled memory includes a first memory die and a second memory die side-by-side formed over a substrate, wherein the first memory die includes a first group of pads and the second memory die includes a second group of pads. The encapsulation package material encloses the non-memory chip and the bundled memory, and the non-memory chip is electronically coupling with the bundled memory through the plurality of pads, the first and the second group of pads. The first group of pads corresponds to the second group of pads by rotating a predetermined degree or by mirror mapping.

System-in-package module and manufacture method for a system-in-package module

The embodiment provides a semiconductor MP wafer process including processing a plurality of MP wafers in a lot or batch with a first process step. The plurality of the MP wafers is split into an MP wafer group-and an MP wafer group-. At least one of the MP wafers of the MP wafer group-is processed with a second process step-and at least one of the MP wafers of the MP wafer group-is processed with a second process step-to form different device components on the MP wafers of the MP wafer group-and group-, respectively. At least one of the MP wafers of the MP wafer group-is processed with a third process step-and at least one of the MP wafers of the MP wafer group-is processed with a third process step-to form a substantially same characteristic device component on the MP wafers.

Semiconductor multi-project or multi-product wafer process

A high speed memory chip module includes a type of memory cell array group and a logic unit. The type memory cell array group includes multiple memory cell array integrated circuits (ICs), and each of the memory cell array ICs has a data bus and at least one memory cell array, and corresponds to first metal-oxide-semiconductor field-effect transistor (MOSFET) gate length corresponding to a first MOSFET process. The logic unit accesses the type of memory cell array group through a first transmission bus, where bus width of the first transmission bus is wider than bus width of the data bus of each of the memory cell array ICs. Corresponding to a second MOSFET process, the logic unit has a second MOSFET gate length which is shorter than the first MOSFET gate length.

High speed memory chip module and electronics system device with a high speed memory chip module

The embodiment provides a semiconductor MP wafer process including processing a plurality of MP wafers in a lot or batch with a first process step. The plurality of the MP wafers is split into an MP wafer group-and an MP wafer group-. At least one of the MP wafers of the MP wafer group-is processed with a second process step-and at least one of the MP wafers of the MP wafer group-is processed with a second process step-to form different device components on the MP wafers of the MP wafer group-and group-, respectively. At least one of the MP wafers of the MP wafer group-is processed with a third process step-and at least one of the MP wafers of the MP wafer group-is processed with a third process step-to form a substantially same device component on the MP wafers.

Growing community of inventors

Hsinchu, Taiwan

Weng-Dah Ken