Taiwan Semiconductor Manufacturing Comp. Ltd.

Weng Chang

Hsin-Yi Lee

Chi On Chui

Cheng-Lung Hung

Syun-Ming Jang Jang

Da-Yuan Lee

Ching-Hwanq Su

Cheng-Yen Tsai

Ji-Cheng Chen

Huicheng Chang

Hsien-Ming Lee

Wei-Chin Lee

Zoe Chen

Kuan-Ting Liu

Chung-Chiang Wu

Chi-On Chui

Hsueh Wen Tsau

Hung-Chin Chung

Ming-Chi Huang

Wei-Jen Lo

Kun-Yu Lee

Ying-Ho Chen

Xiong-Fei Yu

Che-Hao Chang

Hsin-Han Tsai

Yee-Chia Yeo

Tien-I Bao

Chung-Liang Cheng

Ziwei Fang

Ming-Hsing Tsai

Mao-Lin Huang

Liang-Gi Yao

Chia-Ching Lee

Mrunal Abhijith Khaderbad

De-Wei Yu

Peng-Soon Lim

Zhen-Cheng Wu

Chih-Chang Hung

Hsiao-Kuan Wei

Yao-Yi Cheng

Chen-Hua Douglas Yu

Ming-Hua Yu

Hsueh-Chang Sung

Kuan-Yu Chen

Huang-Lin Chao

Tsu Shih

Yi-Hung Lin

Chien-Chang Su

Jih-Churng Twu

Hsien-Hsin Lin

Mong Song Liang

Chun-I Wu

Yen-Tien Tung

Po-Chin Kuo

Chia Ping Lo

Ying-Chieh Hung

JoJo Lee

Chung-Shi Liu

Chao-Cheng Chen

Shih-Chang Chen

Mong-Song Liang

Yu-Lien Huang

Yung-Cheng Lu

Hun-Jan Tao

Ryan Chia-Jen Chen

Da-Wen Lin

Yih-Ann Lin

Lain-Jong Li

Yu Chao Lin

Tzer-Min Shen

Chu-Yun Fu

Cheng-Hung Chang

Chih-Wei Lee

Chi-Chun Chen

Hsiang-Pi Chang

Te-Yang Lai

Shih-Hang Chiu

Chia-Wei Chen

Su-Horng Lin

Kuei-Lun Lin

Chun-Yuan Chou

Jr Jung Lin

Yi-Chen Huang

Shwangming Jeng

Jih-Jse Lin

Hung Chun Tsai

Jo-Chun Hung

Chih-Cheng Lu

Shwang-Ming Cheng

Chen Hua Yu

Yao-Teng Chuang

Tzu-Jen Chou

Cheng Chung Lin

Chia-Ping Lo

Jim Cy Huang

Yi-Lun Li

Bi-Troug Chen

Shwang Ming Jeng

Simon S H Lin

Stacey Fu

Disclosed is a semiconductor device and semiconductor fabrication method. A semiconductor device includes: a gate structure over a semiconductor substrate, having a high-k dielectric layer, a p-type work function layer, an n-type work function layer, a dielectric anti-reaction layer, and a glue layer; and a continuous metal cap over the gate structure formed by metal material being deposited over the gate structure, a portion of the anti-reaction layer being selectively removed, and additional metal material being deposited over the gate structure. A semiconductor fabrication method includes: receiving a gate structure; flattening the top layer of the gate structure; precleaning and pretreating the surface of the gate structure; depositing metal material over the gate structure to form a discontinuous metal cap; selectively removing a portion of the anti-reaction layer; depositing additional metal material over the gate structure to create a continuous metal cap; and containing growth of the metal cap.

Area-selective removal and selective metal cap

A semiconductor device including a substrate, a first transistor and a second transistor is provided. The first transistor includes a first gate structure over the first semiconductor fin. The first gate structure includes a first high-k layer and a first work function layer sequentially disposed on the substrate, a material of the first work function layer may include metal carbide and aluminum, and a content of aluminum in the first work function layer is less than 10% atm. The second transistor includes a second gate structure. The second gate structure includes a second high-k layer and a second work function layer sequentially disposed on the substrate. A work function of the first work function layer is greater than a work function of the second work function layer.

Semiconductor device and method of fabricating the same

Ruthenium of a metal gate (MG) and/or a middle end of line (MEOL) structure is annealed to reduce, or even eliminate, seams after the ruthenium is deposited. Because the annealing reduces (or removes) seams in deposited ruthenium, electrical performance is increased because resistivity of the MG and/or the MEOL structure is decreased. Additionally, for MGs, the annealing generates a more even deposition profile, which results in a timed etching process producing a uniform gate height. As a result, more of the MGs will be functional after etching, which increases yield during production of the electronic device.

Techniques for semiconductor gate and contact formation to reduce seam formation

A method includes forming a dummy gate stack over a semiconductor region, forming a source/drain region on a side of the dummy gate stack, removing the dummy gate stack to form a trench, depositing a gate dielectric layer extending into the trench, depositing a metal-containing layer over the gate dielectric layer, and depositing a silicon-containing layer on the metal-containing layer. The metal-containing layer and the silicon-containing layer in combination act as a work-function layer. A planarization process is performed to remove excess portions of the silicon-containing layer, the metal-containing layer, and the gate dielectric layer, with remaining portions of the silicon-containing layer, the metal-containing layer, and the gate dielectric layer forming a gate stack.

NFET with aluminum-free work-function layer and method forming same

In an embodiment, a device includes: a channel region; a gate dielectric layer on the channel region; a first work function tuning layer on the gate dielectric layer, the first work function tuning layer including a n-type work function metal; a barrier layer on the first work function tuning layer; a second work function tuning layer on the barrier layer, the second work function tuning layer including a p-type work function metal, the p-type work function metal different from the n-type work function metal; and a fill layer on the second work function tuning layer.

Semiconductor device and method

A method includes forming a dummy gate stack over a semiconductor region, forming a source/drain region on a side of the dummy gate stack, removing the dummy gate stack to form a trench, with the semiconductor region being exposed to the trench, forming a gate dielectric layer extending into the trench, and depositing a work-function tuning layer on the gate dielectric layer. The work-function tuning layer comprises aluminum and carbon. The method further includes depositing a p-type work-function layer over the work-function tuning layer, and performing a planarization process to remove excess portions of the p-type work-function layer, the work-function tuning layer, and the gate dielectric layer to form a gate stack.

Work-function layers in the gates of pFETs

Semiconductor devices and methods of manufacturing the semiconductor devices are disclosed herein. The methods include forming nanostructures in a multilayer stack of semiconductor materials. An interlayer dielectric is formed surrounding the nanostructures and a gate dielectric is formed surrounding the interlayer dielectric. A first work function layer is formed over the gate dielectric. Once the first work function layer has been formed, an annealing process is performed on the resulting structure and oxygen is diffused from the gate dielectric into the interlayer dielectric. After performing the annealing process, a second work function layer is formed adjacent the first work function layer. A gate electrode stack of a nano-FET device is formed over the nanostructures by depositing a conductive fill material over the second work function layer.

Semiconductor device and methods of manufacture

A device includes a semiconductor substrate; a vertically stacked set of nanostructures over the semiconductor substrate; a first source/drain region; and a second source/drain region, wherein the vertically stacked set of nanostructures extends between the first source/drain region and the second source/drain region along a first cross-section. The device further includes a gate structure encasing the vertically stacked set of nanostructures along a second cross-section. The second cross-section is along a longitudinal axis of the gate structure. The gate structure comprises: a gate dielectric encasing each of the vertically stacked set of nanostructures; a first metal carbide layer over the gate dielectric; and a gate fill material over the first metal carbide layer. The first metal carbide layer comprises Ce, Hf, V, Nb, Sc, Y, or Mo.

Transistor gate structures and methods of forming thereof

In an embodiment, a device includes: a first nanostructure; a gate dielectric layer around the first nanostructure; a first p-type work function tuning layer on the gate dielectric layer; a dielectric barrier layer on the first p-type work function tuning layer; and a second p-type work function tuning layer on the dielectric barrier layer, the dielectric barrier layer being thinner than the first p-type work function tuning layer and the second p-type work function tuning layer.

Transistor gate structures and methods of forming the same

In an embodiment, a semiconductor device is provided, which includes a first doped gate dielectric layer and a second doped gate dielectric layer, wherein the first doped gate dielectric layer and the second doped gate dielectric layer comprise a high-k material doped with a dipole dopant. The second doped gate dielectric layer has a second concentration of the first dipole dopant. The concentration of the dipole dopant in the first doped gate dielectric layer is greater than the concentration, and the concentration peak of the dipole dopant in the first doped gate dielectric layer is deeper than the concentration peak of the dipole dopant in the second doped gate dielectric layer. A first gate electrode over the first doped gate dielectric layer, and a second gate electrode over the second doped gate dielectric layer, the first gate electrode and the second gate electrode have a same width.

Semiconductor device having doped gate dielectric layer and method for forming the same

The present disclosure provides a semiconductor structure and a method for forming the same. The semiconductor structure includes a first nanosheet channel structure and a first high-k dielectric layer surrounding the first nanosheet channel structure. In addition, the semiconductor structure includes a second nanosheet channel structure disposed above and substantially parallel to the first nanosheet channel structure, and a second high-k dielectric layer surrounding the second nanosheet channel structure. The semiconductor structure further includes a work function adjustment layer including silicon and disposed between the first high-k dielectric layer and the second high-k dielectric layer. The first high-k dielectric layer and the second high-k dielectric layer are separated by the work function adjustment layer.

Semiconductor structure including nanosheet channel structure and method for forming the same

A semiconductor device includes a fin protruding above a substrate; source/drain regions over the fin; nanosheets between the source/drain regions; and a gate structure over the fin and between the source/drain regions. The gate structure includes: a gate dielectric material around each of the nanosheets; a first liner material around the gate dielectric material; a work function material around the first liner material; a second liner material around the work function material; and a gate electrode material around at least portions of the second liner material.

Nanosheet field-effect transistor device and method of forming

A semiconductor device and a method of forming the same are provided. The method includes forming a fin extending from a substrate. A dummy gate is formed over the fin. The dummy gate extends along sidewalls and a top surface of the fin. The dummy gate is removed to form a recess. A replacement gate is formed in the recess. Forming the replacement gate includes forming an interfacial layer along sidewalls and a bottom of the recess. A dipole layer is formed over the interfacial layer. The dipole layer includes metal atoms. Fluorine atoms are incorporated in the dipole layer. The fluorine atoms and the metal atoms are driven from the dipole layer into the interfacial layer. The dipole layer is removed.

Gate structure of semiconductor device and method of forming same

A method includes forming a gate dielectric on a semiconductor region, depositing a work-function layer over the gate dielectric, depositing a silicon layer over the work-function layer, and depositing a glue layer over the silicon layer. The work-function layer, the silicon layer, and the glue layer are in-situ deposited. The method further includes depositing a filling-metal over the glue layer; and performing a planarization process, wherein remaining portions of the glue layer, the silicon layer, and the work-function layer form portions of a gate electrode.

In-situ formation of metal gate modulators

A method includes forming a dummy gate stack over a semiconductor region, forming epitaxial source/drain regions on opposite sides of the dummy gate stack, removing the dummy gate stack to form a trench, depositing a gate dielectric layer extending into the trench, and depositing a work-function layer over the gate dielectric layer. The work-function layer comprises a seam therein. A silicon-containing layer is deposited to fill the seam. A planarization process is performed to remove excess portions of the silicon-containing layer, the work-function layer, and the gate dielectric layer. Remaining portions of the silicon-containing layer, the work-function layer, and the gate dielectric layer form a gate stack.

Seam-filling of metal gates with Si-containing layers

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Hsin-Chu, Taiwan

Weng Chang