United Microelectronics Corp.

Macronix International Co., Ltd.

Novatek Microelectronics Corp.

Industrial Technology Research Institute

Other

Wen-Yi Hsieh

Tri-Rung Yew

Kuo-Tai Huang

Kun-Chih Wang

Water Lur

Chun-Hsiung Hung

Ken-Hui Chen

Chih-Chien Liu

Ching-Chung Lin

Jenn-Tarng Lin

Edberg Fang

Teng-Chun Tsai

Nai-Ping Kuo

Yimin Huang

Tung-Po Chen

Cheng-Yuan Tsai

Cha-Hsin Lin

Gwo-Shii Yang

Hong-Tsz Pan

Zing-Way Pei

Hsiao-Ling Lu

Chi-Rong Lin

Po-Ying Chen

Shing-Chii Lu

Kevin Hsieh

Han-Sung Chen

Jhih-Siou Cheng

Ju-Lin Huang

Juan-Yuan Wu

Yuan-Ching Peng

Shih-Wei Sun

Ming-Sheng Yang

Wen-Kuan Yeh

Keko-Chun Liang

Huang-Chin Tang

Fang-Ching Chao

Wei-Lun Shih

Horng-Bor Lu

Huan-Teng Cheng

Hsiao-Pang Chou

Chih-hsun Chu

Ting-Hsuan Hung

Horng-Nan Chern

Chuan-Ying Yu

Lih-Juann Chen

Chiung-Sheng Hsiung

Yong-fen Hsieh

Tsu-An Lin

Michael W C Huang

Kevin Lin

Wu Wei Lin

Yufe Feng Lin

Hsu-Chih Wei

Li-Yeat Chen

Jui-Chan Chang

Se-Chueh Lo

Nai-Pin Kuo

Heinz Shih

L Y Chen

Michael Wc Huang

James Cc Huang

Hung-Yi Huang

The present invention discloses a display panel and a display device. The display panel comprises a plurality of common electrode blocks and a plurality of display regions. During a display period, one or more common electrode blocks corresponding to one of the display regions which is to be displayed during the display period are coupled to a common voltage; and during the display period, one or more of the common electrode blocks corresponding to the display regions which are not to be displayed during the display period are kept in a floating state.

Display panel, display device and driving method

In the invention, a fingerprint driving circuit, a fingerprint sensing device, an electronic apparatus, and an operation method of the fingerprint sensing device are provided. By keeping fingerprint sensing lines in a non-fingerprint sensing region in an electrically non-floating state, flash phenomenon in a display panel may be avoided.

Fingerprint driving circuit, fingerprint sensing device, electronic apparatus and operation method

The present invention discloses a touch display driving device and a driving method in the same. The touch display driving device is used for driving a touch display panel, the touch display panel comprising a plurality of common electrode blocks and a plurality of display regions. The touch display driving device comprising a multiplexing circuit which is configured to: during a display period, couple one or more common electrode blocks corresponding to one of the display regions which is to be displayed during the display period to a first voltage; and during the display period, couple one or more of the common electrode blocks corresponding to the display regions which are not to be displayed during the display period to a second voltage.

Touch display driving device and driving method in the same

An integrated circuit and a touch display apparatus are provided. The integrated circuit is configured to drive a touch display panel. The integrated circuit includes a regulator. An output terminal of the regulator is employed as a first node to output a common voltage, wherein the common voltage is configured to be provided to at least one common electrode of the touch display panel. An input terminal of the regulator is coupled to a second node different from the first node to receive a feedback voltage.

Integrated circuit and touch display apparatus to shorten a settle time of a common electrode of a touch display panel

An embodiment of the invention provides a memory array including a plurality of bit lines, a plurality of memory cells and a device. Each of the plurality of memory cells has a first node, a second node and a third node, wherein the third node is coupled to one of the plurality of bit lines. The device couples the plurality of bit lines together to form a common node for one of the plurality of memory cells.

Memory array and method of operating one of a plurality of memory cells

A memory device is disclosed that includes a plurality of word lines and a plurality of memory cells operating in one of a plurality of modes and coupled to at least one of the word lines. The memory device also includes a plurality of reference lines and reference cells. Each reference cell corresponds to one of the operating modes, supplies a reference current for the corresponding mode, and is coupled to at least one of the reference lines. A reference cell current from a reference cell can also be compared to a target range and, if outside the target range, the voltage level on a corresponding reference line can be adjusted accordingly such that the reference current falls within the target range (i.e., reference current trimming).

Memory devices and methods using improved reference cell trimming algorithms for accurate read operation window control

A NROM memory device includes an array of memory cells and first and second bit lines. The first and second bit lines are coupled to opposite sides of the memory cells. During an erase operation, one of the sides of the memory cells receives a positive voltage and the other side couples to a common node or a limited current source. Methods are also disclosed that can easily screen for marginal memory cells based on a threshold voltage distribution of the memory cells.

Nitride read-only memory cell and nitride read-only memory array

Devices and methods to improve erase uniformity and to screen for marginal cells for NROM memories

A method for fabricating semiconductor device is provided. A high stress layer formed on, under or on both sides of the transistors of the semiconductor device is employed as a cap layer. A specific region is then defined through photo resistor mask, and the stress of the region is changed by ion implanting. Therefore, compressive stress and tensile stress occur on the high stress layer. According the disclosed method, the high stress layer may simultaneously improve the characteristics of the transistors formed on the same wafer. Further, the mobility of the carriers of the device is enhanced.

Method of making semiconductor devices

A program verification method for a memory device having a virtual array including a plurality of memory cells determines if leakage current passes through one or more neighboring memory cells to the programmed memory cell. The programmed memory cell is verified based on a first threshold state if leakage current is determined to pass through one or more neighboring memory cells. The programmed memory cell is verified based on a second threshold state if the leakage current is not determined to pass through one or more neighboring memory cells.

Memory device having a virtual ground array and methods using program algorithm to improve read margin loss

A current produced by a current mirror in a clock generator circuit for a charge pump is controlled by a temperature dependent, current-adjusting MOSFET which has a threshold voltage (Vt) that varies with temperature. As the temperature varies, the current through the a temperature dependent, current-adjusting MOSFET varies, to thereby control a frequency of the clock generator circuit. The MOSFET can be provided with a temperature-independent power supply, so that the current of the temperature dependent, current-adjusting MOSFET can be more closely controlled.

Charge pump system and clock generator

The present invention provides a method for forming low dielectric constant layer in a semiconductor device comprising providing the semiconductor device. A dielectric layer is formed on the semiconductor device, which has a constituent of a plurality of unsaturated carbon bonds compounds. The dielectric layer is then treated with hydrogen. The purpose of treatment of hydrogen is to form saturated carbon bonds compounds for unexhausted unsaturated carbon bonds in the dielectric layer.

Method for forming low dielectric constant layer

A method of fabricating a DRAM capacitor uses tungsten nitride in the process of forming a capacitor. The structure of the capacitor is simple and the process is easily executed. Furthermore, the invention provides a method of forming tungsten nitride, comprising a step of implanting nitrogen into a tungsten silicide layer and a step of executing a rapid thermal process under ammonia gas to form a tungsten nitride layer on the surface of the tungsten silicide layer. The method of fabricating a DRAM capacitor comprises forming the tungsten silicide layer after forming a part smaller than a bottom electrode of the capacitor from doped polysilicon and forming tungsten nitride on the surface of the tungsten nitride layer.

Method of fabricating DRAM capacitor

A method for manufacturing the lower electrode of a DRAM capacitor. The method includes depositing polysilicon instead of amorphous silicon to form the lower electrode. Because polysilicon has a higher depositing temperature, it has a higher depositing rate capable of shortening depositing time. After forming the polysilicon lower electrode, the upper portion of the polysilicon layer is transformed into an amorphous layer by bombarding the polysilicon layer with ions to damage its internal structure. Eventually, hemispherical grain silicon is able to grow over the lower electrode, thereby increasing its surface area.

Method for manufacturing lower electrode of DRAM capacitor

Growing community of inventors

Hsinchu, Taiwan

Wen-Yi Hsieh