Taiwan Semiconductor Manufacturing Comp. Ltd.

Industrial Technology Research Institute

Wen-Yao Chang

Shang-Yun Hou

Sung-Hui Huang

Kuan-Yu Huang

Yu-Jen Cheng

Kewei Zuo

Chien Rhone Wang

Yu-Yun Huang

Shu Chia Hsu

Chen-Hua Douglas Yu

Chung-Shi Liu

Tzxy-Chui Wang

Wu-Hsiung Fu

Man Tzou

In an embodiment, an interposer has a first side, a first integrated circuit device attached to the first side of the interposer with a first set of conductive connectors, each of the first set of conductive connectors having a first height, a first die package attached to the first side of the interposer with a second set of conductive connectors, the second set of conductive connectors including a first conductive connector and a second conductive connector, the first conductive connector having a second height, the second conductive connector having a third height, the third height being different than the second height, a first dummy conductive connector being between the first side of the interposer and the first die package, an underfill disposed beneath the first integrated circuit device and the first die package, and an encapsulant disposed around the first integrated circuit device and the first die package.

Semiconductor die package and method of manufacture

A method includes recording a wafer ID and a location ID of a device die in a database, and bonding the device die over a package substrate, wherein the device die and the package substrate are disposed in a package. A package ID is on the package. A mapping is established to link the wafer ID and the location ID of the device die to the package ID.

Die-tracing in integrated circuit manufacturing and packaging

In a reflow process, a plurality of solder bumps between a first workpiece and a second workpiece is melted. During a solidification stage of the plurality of solder bumps, the plurality of solder bumps is cooled at a first cooling rate. After the solidification stage is finished, the plurality of solder bumps is cooled at a second cooling rate lower than the first cooling rate.

Solder joint reflow process for reducing packaging failure rate

A method of evaluating and optimizing performance of a chiller system includes the following steps. Determine a number of activated chillers, a number of activated cooling towers, and the lowest outlet temperature of cooling water of a cooling tower as an operating settings. By developing evaluating models, sequentially determine a temperature of the cooling water entering the chillers, a total power consumption of chillers, a total power consumption of the cooling towers, and a total power consumption of pumping cooling water. Then, determine a total power consumption of the system by the sum of the total power consumption of the chillers, the total power consumption of the cooling towers, and the total power consumption of pumping cooling water. Through the above method, the system total power consumptions under different operating settings are evaluated, so as to determine an optimized operating setting to optimize the performance of the system.

Method for evaluating and optimizing performance of chiller system

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Hsinchu, Taiwan

Wen-Yao Chang