Taiwan Semiconductor Manufacturing Comp. Ltd.

Wen-Ting Chu

Yu-Wen Liao

Kuo-Chi Tu

Chih-Yang Chang

Chin-Chieh Yang

Hsia-Wei Chen

Sheng-Hung Shih

Jen-Sheng Yang

Chia-Ta Hsieh

Di-Son Kuo

Yong-Shiuan Tsair

Tzu-Yu Chen

Wen-Chun You

Fu-Chen Chang

Hung-Cheng Sung

Chia-Shiung Tsai

Tong-Chern Ong

Cheng-Yuan Tsai

Hsing-Lien Lin

Chrong-Jung Lin

Chung-Cheng Chou

Jack Yeh

Shih-Chang Liu

Chieh-Fei Chiu

Yue-Der Chih

Hai-Dang Trinh

Chih-Hsiang Chang

Chu-Jie Huang

Yu-Der Chih

Kuo-Ching Huang

Yai-Fen Lin

Hung-Der Su

Chun-Yang Tsai

Jong Chen

I-Ching Chen

Chuan-Li Chang

Hung Cho Wang

Fu-Ting Sung

Sheng-Huang Huang

Chi-Hsin Lo

Kuei-Hung Shen

Kuo-Yuan Tu

Chuang-Ke Yeh

Yi-Shing Chang

Manish Kumar Singh

Nai-Chao Su

Tung-Sheng Hsiao

Harry-Hak-Lay Chuang

Po-Hao Tseng

Ching-Pei Hsieh

Chao-Yang Chen

Cheng-Jun Wu

Chin-Yu Mei

Yeur-Luen Tu

Ying-Lang Wang

Chia-Fu Lee

Chen-Ming Huang

Po-Wei Liu

Wen-Tuo Huang

Ya-Chen Kao

Chrong Jung Lin

Yvonne Lin

Trinh Hai Dang

Chang-Jen Hsieh

Chang-Sheng Liao

Chi-Tsai Chen

Chung-Li Chang

Chung-Yi Yu

Chung-Cheng Wu

Hsin-Ming Chen

Yu-Wei Ting

Shine Chung

Chia-Wei Liu

Fa-Shen Jiang

Po-Hao Lee

Yu-Ling Hsu

Ming-Chou Ho

Wei-Ming Wang

Yu-Hsiung Wang

Chih-Hung Pan

Yu-Hsiang Yang

Chang-Song Lin

Eric Chen

Hsien-Wei Chin

Tzu-Hsuan Yeh

Pili Huang

Yi-Chieh Chiu

Alexander Kalnitsky

Chih-Ming Chen

Chang-Ming Wu

Ru-Liang Lee

Shih-Chi Fu

Cheng-Hsiung Kuo

Chin-Wei Liang

Shih-Wei Wang

Yu-Hsing Chang

Mo-Chiun Yu

Te-Hsun Hsu

Jih-Chen Wang

The present disclosure relates to an integrated chip. The integrated chip includes a bottom electrode disposed over a substrate. The bottom electrode has a first thickness along an outermost edge and a second thickness between the outermost edge and a lateral center of the bottom electrode. The first thickness is larger than the second thickness. A data storage structure is over the bottom electrode and a top electrode is over the data storage structure.

Memory device

A semiconductor structure includes a first electrode comprising a first metallic material; a memory film including at least one dielectric metal oxide material and contacting the first electrode; and a second electrode comprising a second metallic material and contacting the memory film. The memory film includes a center region having a first average atomic ratio of a passivation element to oxygen that is less than 0.01, and includes a peripheral region having a second average atomic ratio of the passivation element to oxygen that is greater than 0.05.

RRAM with post-patterned treated memory films to provide improved endurance characteristics and methods for forming

Various embodiments of the present disclosure are directed towards a memory cell comprising a high electron affinity dielectric layer at a bottom electrode. The high electron affinity dielectric layer is one of multiple different dielectric layers vertically stacked between the bottom electrode and a top electrode overlying the bottom electrode. Further, the high electrode electron affinity dielectric layer has a highest electron affinity amongst the multiple different dielectric layers and is closest to the bottom electrode. The different dielectric layers are different in terms of material systems and/or material compositions. It has been appreciated that by arranging the high electron affinity dielectric layer closest to the bottom electrode, the likelihood of the memory cell becoming stuck during cycling is reduced at least when the memory cell is RRAM. Hence, the likelihood of a hard reset/failure bit is reduced.

High electron affinity dielectric layer to improve cycling

An integrated circuit device has an RRAM cell that includes a top electrode, an RRAM dielectric layer, and a bottom electrode having a surface that interfaces with the RRAM dielectric layer. Oxides of the bottom electrode are substantially absent from the bottom electrode surface. The bottom electrode has a higher density in a zone adjacent the surface as compared to a bulk region of the bottom electrode. The surface has a roughness Ra of 2 nm or less. A process for forming the surface includes chemical mechanical polishing followed by hydrofluoric acid etching followed by argon ion bombardment. An array of RRAM cells formed by this process is superior in terms of narrow distribution and high separation between low and high resistance states.

RRAM bottom electrode

A memory device includes a bottom electrode, a buffer element, a metal-containing oxide portion, a resistance switch element, and a top electrode. The buffer element is over the bottom electrode. The metal-containing oxide portion is over the buffer element, in which the metal-containing oxide portion has a same metal material as that of the buffer element. The resistance switch element is over the metal-containing oxide portion. The top electrode is over the resistance switch element.

Memory device with bottom electrode

The present disclosure relates to an integrated chip structure. The integrated chip structure includes a first source/drain region and a second source/drain region disposed within a substrate. A select gate is over the substrate between the first source/drain region and the second source/drain region. A ferroelectric random access memory (FeRAM) device is over the substrate between the select gate and the first source/drain region. A transistor device is disposed on an upper surface of the substrate. The substrate has a recessed surface that is below the upper surface of the substrate and that is laterally separated from the upper surface of the substrate by a boundary isolation structure extending into a trench within the upper surface of the substrate. The FeRAM device is arranged over the recessed surface.

Embedded ferroelectric memory cell

A memory architecture includes: a plurality of cell arrays each of which comprises a plurality of bit cells, wherein each of bit cells of the plurality of cell arrays uses a respective variable resistance dielectric layer to transition between first and second logic states; and a control logic circuit, coupled to the plurality of cell arrays, and configured to cause a first information bit to be written into respective bit cells of a pair of cell arrays as an original logic state of the first information bit and a logically complementary logic state of the first information bit, wherein the respective variable resistance dielectric layers are formed by using a same recipe of deposition equipment and have different diameters.

Resistive random access memory device

Some embodiments relate to an integrated circuit including one or more memory cells arranged over a semiconductor substrate between an upper metal interconnect layer and a lower metal interconnect layer. A memory cell includes a bottom electrode disposed over the lower metal interconnect layer, a data storage or dielectric layer disposed over the bottom electrode, and a top electrode disposed over the data storage or dielectric layer. An upper surface of the top electrode is in direct contact with the upper metal interconnect layer without a via or contact coupling the upper surface of the top electrode to the upper metal interconnect layer. Sidewall spacers are arranged along sidewalls of the top electrode, and have bottom surfaces that rest on an upper surface of the data storage or dielectric layer.

Metal landing on top electrode of RRAM

A memory device includes a first bottom electrode, a first memory stack, and a second memory stack. The first bottom electrode has a first portion and a second portion connected to the first portion. The first memory stack is over the first portion of the first bottom electrode. The first memory stack includes a first resistive switching element and a first top electrode over the first resistive switching element. The second memory stack is over the second portion of the first bottom electrode. The second memory stack comprises a second resistive switching element and a second top electrode over the second resistive switching element.

Memory device having two memory stacks over one bottom electrode

A method for fabricating an integrated circuit is provided. The method includes depositing a dielectric layer over a conductive feature; etching an opening in the dielectric layer to expose the conductive feature, such that the dielectric layer has a tapered sidewall surrounding the opening; depositing a bottom electrode layer into the opening in the dielectric layer; depositing a resistance switch layer over the bottom electrode layer; patterning the resistance switch layer and the bottom electrode layer respectively into a resistance switch element and a bottom electrode, in which a sidewall of the bottom electrode is landing on the tapered sidewall of the dielectric layer.

Integrated circuit

An integrated circuit device includes an interconnect layer, a memory structure, a third conductive feature, and a fourth conductive feature. The interconnect layer includes a first conductive feature and a second conductive feature. The memory structure is over and in contact with the first conductive feature. The memory structure includes at least a resistance switching element over the first conductive feature. The third conductive feature, including a first conductive line, is over and in contact with the second conductive feature. The fourth conductive feature is over and in contact with the memory structure. The fourth conductive feature includes a second conductive line, a top surface of the first conductive line is substantially level with a top surface of the second conductive line, and a bottom surface of the first conductive line is lower than a bottommost portion of a bottom surface of the second conductive line.

Integrated circuit device

In some embodiments, the present disclosure relates to a method of forming an integrated chip including forming a ferroelectric layer over a bottom electrode layer, forming a top electrode layer over the ferroelectric layer, performing a first removal process to remove peripheral portions of the bottom electrode layer, the ferroelectric layer, and the top electrode layer, and performing a second removal process using a second etch that is selective to the bottom electrode layer and the top electrode layer to remove portions of the bottom electrode layer and the top electrode layer, so that after the second removal process the ferroelectric layer has a surface that protrudes past a surface of the bottom electrode layer and the top electrode layer.

FeRAM MFM structure with selective electrode etch

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a memory device arranged over an etch stop material over a substrate. The memory device includes a data storage structure disposed between a bottom electrode and a top electrode. A first interconnect via contacts an upper surface of the bottom electrode and a second interconnect via contacts an upper surface of the top electrode. An interconnect wire contacts a top of the first interconnect via. A third interconnect via contacts a bottom of the interconnect wire and extends through the etch stop material to a plurality of lower interconnects below the etch stop material.

Memory structure

Various embodiments of the present application are directed a memory layout for reduced line loading. In some embodiments, a memory device comprises an array of bit cells, a first conductive line, a second conductive line, and a plurality of conductive bridges. The first and second conductive lines may, for example, be source lines or some other conductive lines. The array of bit cells comprises a plurality of rows and a plurality of columns, and the plurality of columns comprise a first column and a second column. The first conductive line extends along the first column and is electrically coupled to bit cells in the first column. The second conductive line extends along the second column and is electrically coupled to bit cells in the second column. The conductive bridges extend from the first conductive line to the second conductive line and electrically couple the first and second conductive lines together.

Memory layout for reduced line loading

A semiconductor device includes a bottom electrode, a top electrode, a sidewall spacer, and a data storage element. The sidewall spacer is disposed aside the top electrode. The data storage element is located between the bottom electrode and the top electrode, and includes a ferroelectric material. The data storage element has a peripheral region which is disposed beneath the sidewall spacer and which has at least 60% of ferroelectric phase. A method for manufacturing the semiconductor device and a method for transforming a non-ferroelectric phase of a ferroelectric material to a ferroelectric phase are also disclosed.

Semiconductor device and method for manufacturing the same

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Kaohsiung, Taiwan

Wen-Ting Chu