United Microelectronics Corp.

United Silicon Incorporated

Wen-Shan Wei

Hsi-Mao Hsiao

Chun-Lung Chen

Tong-Hsin Lee

Wen-Sheng Chien

Chia-Fu Yeh

Jui-Chun Kuo

Ming-Sheng Kuo

H C Yu

In accordance with the present invention, a method is provided for dry cleaning a processing chamber. This method comprises the step of introducing a first cleaning process gas into the processing chamber. A plasma is formed from the first cleaning process gas and maintained for a first time period. Next, repeating the step of introducing the cleaning process gas, a second cleaning process gas is introduced into the processing chamber and maintained the plasma for a second time period. As a result, the present invention is capable of removing polymer built up on the processing chamber's interior surfaces to achieve a high yield and maintaining throughput of the substrates in the plasma processing system.

Method for dry cleaning metal etching chamber

The invention describes a method for fabricating an inter-layer dielectric layer. In this method, a plurality of first polysilicon lines, a first inter-layer dielectric layer, and a plurality of second polysilicon lines are formed in sequence on the substrate. A second inter-layer dielectric layer is formed between the plurality of second polysilicon lines and entirely covers the plurality of second polysilicon lines. Afterwards, a spin-on glass layer is formed on the second inter-layer dielectric layer, and then, while using the upper surfaces of the second polysilicon lines as etch end points, the spin-on glass layer and the second inter-layer dielectric layer are etched back to entirely remove the spin-on glass layer and partially remove the second inter-layer dielectric layer over the second polysilicon lines. Subsequently, a cover layer is formed to cover the second polysilicon lines and the remainder of the inter-layer dielectric layer. Finally, an oxide layer is formed to cover the resulting structure.

Method for forming an inter-layer dielectric layer

A method of fabricating a lower electrode of a capacitor. A sacrificial multilayer is formed on a semiconductor layer. The sacrificial multi-layer is a stack of alternating first and second sacrificial layers. A patterned first mask layer having a first opening above a conductive plug in the semiconductor substrate is formed on the sacrificial multi-layer. A planar spacer is formed on the sidewall of the first opening. A second mask layer is formed to fill the first opening. The planar spacer and the sacrificial multi-layer thereunder are anisotropically etched until the semiconductor substrate is exposed to form a second opening while using the first mask layer and second mask layer as a mask. The first sacrificial layers exposed by the second opening are isotropically etched to form a plurality of recesses. The second opening and the recesses are filled with a conductive material layer. Finally, the first mask layer, second mask layer, and sacrificial multi-layer are removed.

Method of fabricating a lower electrode of capacitor

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Taipei, Taiwan

Wen-Shan Wei