Advanced Semiconductor Engineering, Inc.

Wen-Pin Huang

Li-Hua Tai

Pai-Chou Liu

Fu Tang Chu

Yan Ting Shen

Sung-Ching Hung

Bo Hua Chen

Yun-Chih Fei

Sheng-Hong Zheng

Su Tao

Ho-Ming Tong

Chun-Chi Lee

Po-Jen Cheng

Chih-Huang Chang

Jeng-Da Wu

William Tze-You Chen

Yueh-Ju Lin

Wen Shang Chang

A wafer supporting mechanism and a method for wafer dicing are provided. The wafer supporting mechanism includes a base portion and a support portion. The base portion includes a first gas channel and a first outlet connected to the first gas channel. The support portion is connected to the base portion and including a second gas channel connected to the first gas channel. An accommodation space is defined by the base portion and the support portion.

Wafer supporting mechanism and method for wafer dicing

A semiconductor device package includes a substrate, a first electronic component, a second electronic component, a package body and a shield. The substrate has a first surface and a second surface opposite to the first surface. The substrate defines a cavity from the second surface extending into the substrate. The first electronic component is disposed on the first surface of the substrate. The second electronic component is disposed within the cavity of the substrate. The package body is disposed on a portion of the first surface of the substrate and covers the first electronic component. The shield is disposed on external surfaces of the package body.

Semiconductor device package and method of manufacturing the same

The present disclosure provides a semiconductor device package. The semiconductor device package includes a first substrate and a second substrate. The first substrate has a first surface and a second surface opposite to the first surface of the first substrate. The second substrate has a first surface facing the first substrate and a second surface opposite to the first surface of the second substrate. The semiconductor device package also includes a first electronic component disposed on the first surface of the second substrate and electrically connected to the first surface of the second substrate. The semiconductor device package also includes a first encapsulant and a second encapsulant between the first substrate and the second substrate. The first encapsulant is different from the second encapsulant. A method of manufacturing a semiconductor device package is also disclosed.

Semiconductor device package

A semiconductor device package includes a first carrier, a first electronic component, a second electronic component, a second carrier and an electrical connection structure. The first carrier has a first surface and a second surface opposite to the first surface. The first electronic component is disposed on the first surface of the first carrier. The second electronic component is disposed on the second surface of the first carrier. The second carrier has a first surface facing the second surface of the first carrier and a second surface opposite to the first surface. The electrical connection structure is electrically connecting the first carrier with the second carrier.

The present invention relates to a semiconductor package, comprising a carrier, a semiconductor device, a first wire and a second wire. The carrier has a first electrically connecting portion and a second electrically connecting portion. The semiconductor device has a plurality of pads. The first wire electrically connects one of the pads of the semiconductor device and the first electrically connecting portion of the carrier, and the first wire has a first length. The second wire electrically connects one of the pads of the semiconductor device and the second electrically connecting portion of the carrier, and the second wire has a second length. The second length is larger than the first length, and the diameter of the second wire is larger than that of the first wire. Thus, the material usage for the wire is reduced, and the manufacturing cost is reduced.

Semiconductor package

A stacked semiconductor package, includes a carrier, a first semiconductor device, a second semiconductor device, a plurality of first wires and a plurality of second wires. The carrier has a plurality of electrically connecting portions. The first semiconductor device has a plurality of first pads. The second semiconductor device has a plurality of second pads. The second semiconductor device is disposed on the first semiconductor device. The first wires electrically connect the first pads of the first semiconductor device and the electrically connecting portions of the carrier, and the second wires electrically connect the second pads of the second semiconductor device and the electrically connecting portions of the carrier. The diameters of the second wires are larger than those of the first wires. Thus, the material of the wires is reduced, and the manufacturing cost is reduced.

Stacked semiconductor package

A bump structure on a contact pad and a fabricating process thereof. The bump comprises an under-ball-metallurgy layer, a bonding mass and a welding lump. The under-ball-metallurgy layer is formed over the contact pad and the bonding mass is formed over the under-ball-metallurgy layer by conducting a pressure bonding process. The bonding mass having a thickness between 4 to 10 &#x3bc;m is made from a material such as copper. The welding lump is formed over the bonding mass such that a sidewall of the bonding mass is also enclosed.

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Kaohsiung, Taiwan

Wen-Pin Huang