Taiwan Semiconductor Manufacturing Comp. Ltd.

Wen-Kung Cheng

Ying-Lang Wang

Yi-Lung Cheng

Chi-Wen Liu

Shih-Chi Lin

Hung-Ju Chien

Chun-Ching Tsan

Jiann-Kwang Wang

Yin-Lang Wang

Ming-Hua Yoo

Szu-An Wu

Chung-Shi Liu

Syun-Ming Jang Jang

Tien-I Bao

Chung-Long Chang

Chyi-Tsong Ni

Yuan-Hung Chiu

Chen-Peng Fan

Ying-Hsiang Chen

Ming-Hsien Chen

Jane-Bai Lai

Yao Hsiang Liang

Hui-Ling Wang

Chao-Keng Li

Ming-Hwa Yoo

Ping-Yuan Chen

Jung-Chen Yang

Pei-Fen Chou

Sez-An Wu

Richard Chen

Wen-Yu Ho

Yong-Sin Chang

Jin-Chang Chen

Labo Chang

Szu-Au Wu

Huai-Te Huang

Shin-Chi Lin

Yi-Lung Wang

Ying-Long Wang

In accordance with some embodiments, systems and methods for processing a semiconductor substrate are provided. The method includes loading a semiconductor substrate from a chamber to a transfer module, detecting a center and a notch of the semiconductor substrate by the transfer module, and transferring the semiconductor substrate from the transfer module to a process chamber.

Systems and method for transferring a semiconductor substrate

A semiconductor structure includes a transistor formed over a substrate. The transistor includes a transistor gate and at least one source/drain region. The semiconductor structure includes a pre-determined region coupled to the transistor. The semiconductor structure further includes a resist protection oxide (RPO) layer formed over the pre-determined region, wherein the RPO layer has a level of nitrogen of about 0.35 atomic % or less.

Image sensor having an RPO layer containing nitrogen

Two problems seen in CMP as currently executed are a tendency for slurry particles to remain on the surface and the formation of a final layer of oxide. These problems have been solved by adding to the slurry a quantity of TMAH or TBAH. This has the effect of rendering the surface being polished hydrophobic. In that state a residual layer of oxide will not be left on the surface at the conclusion of CMP. Nor will many slurry abrasive particles remain cling to the freshly polished surface. Those that do are readily removed by a simple rinse or buffing. As an alternative, the CMP process may be performed in three stages&#x2014;first convention CMP, then polishing in a solution of TMAH or TBAH, and finally a gentle rinse or buffing.

CMP process leaving no residual oxide layer or slurry particles

A method of depositing a plasma enhanced CVD metal nitride layer over an exposed copper surface in a semiconductor wafer manufacturing process to improve the metal nitride layer adhesion and to reduce copper hillock formation including providing a process surface which is an exposed copper surface; preheating the process surface; plasma sputtering the exposed copper surface in-situ to remove copper oxides; and, depositing a metal nitride layer in-situ according to a plasma enhanced CVD process at a selected deposition pressure to reduce plasma ion bombardment energy transfer and to suppress-copper hillock formation.

Method of forming a metal nitride layer over exposed copper

Two problems seen in CMP as currently executed are a tendency for slurry particles to remain on the surface and the formation of a final layer of oxide. These problems have been solved by adding to the slurry a quantity of TMAH or TBAH. This has the effect of rendering the surface being polished hydrophobic. In that state a residual layer of oxide will not be left on the surface at the conclusion of CMP. Nor will many slurry abrasive particles remain cling to the freshly polished surface. Those that do are readily removed by a simple rinse or buffing. As an alternative, the CMP process may be performed in three stages&mdash;first convention CMP, then polishing in a solution of TMAH or TBAH, and finally a gentle rinse or buffing.

A method of removing residual fluorine present in a HDP-CVD chamber which includes a high pressure seasoning process, a dry-cleaning process, and a low-pressure deposition process.

Method for removing residual fluorine in HDP-CVD chamber

A method for cleaning residual material from a chemical vapor deposition (CVD) apparatus in situ employing dry etching. There is first employed a high density plasma chemical vapor deposition (HDP-CVD) method to deposit layers of silicon oxide material upon substrates within a chemical vapor deposition reactor apparatus. After removal of substrates, the reactor chamber is closed off. The interior of the reactor is then filled with a gas and a plasma formed therewithin, to which oxygen is added and the reactor allowed to come to an increased temperature and bake for a period of time. The reactor power is then turned off and the reactor evacuated. There is then carried out a normal cleaning step within the reactor chamber employing a reactive gas such as NF , with greater cleaning efficiency due to the increased temperature caused by the baking step.

Method for improved cleaning in HDP-CVD process with reduced NF3 usage

An improved and new process for separating a substrate from a wetted polishing pad in a CMP apparatus has been developed. Following CMP the polishing pad is wetted with a low surface tension liquid and the substrate is moved across the surface of the polishing pad to cause the interface between the substrate and the polishing pad to be wetted with the low surface tension liquid. The force required to cause separation of the substrate from the polishing pad wetted with said low surface tension liquid is reduced by a factor of about 10 to 30% and the breakage of fragile semiconductor wafer substrates during the unloading operation is markedly reduced. Suitable low surface tension liquids are water at a temperature between about 50&deg; C. and 80&deg; C., or solutions of water with long chain surfactants, such as poly-acrylate, poly-vinyl alcohol, butanol, pantanol or isopropol alcohol.

Method of unloading substrates in chemical-mechanical polishing apparatus

A template for measuring the edge width on a disk that is not covered by a coating layer on a top surface of the disk and a method for using such template are disclosed. The template is made of a substantially transparent sheet that has a contour substantially the same as the contour of the disk to be measured. A series of marks are provided on a top surface of the sheet along a peripheral edge of the sheet at numerous predetermined distances from the peripheral edge. The marks may be provided in scribed thin lines, or the marks may be provided in scribed thin lines that are color coded for easier identification purpose. The present invention novel template can be most suitably used on a silicon wafer of any size. However, it can also be used on a disk of any shape or contour to produce the same desirable result.

Template for measuring edge width and method of using

A method for forming a patterned reflective layer first employs a substrate. There is then formed over the substrate a blanket reflective layer. There is then formed upon the blanket reflective layer an anti-reflective coating (ARC) layer formed employing a plasma enhanced chemical vapor deposition (PECVD) method employing a deposition gas composition comprising silane, nitrous oxide and argon. There is then formed upon the blanket anti-reflective coating (ARC) layer a blanket photoresist layer. There is then photoexposed and developed the blanket photoresist layer to form a patterned photoresist layer. There is then etched, while employing a first etch method, the blanket anti-reflective coating (ARC) layer to form a patterned anti-reflective coating (ARC) layer while employing the patterned photoresist layer as a first etch mask layer. Finally, there is then etched, while employing a second etch method, the blanket reflective layer to form the patterned reflective layer while employing at least the patterned anti-reflective coating (ARC) layer as a second etch mask layer.

Method for forming anti-reflective coating layer with enhanced film thickness uniformity

A new method of forming a plasma-enhanced silicon-rich oxynitride layer having improved uniformity across the wafer in terms of layer thickness, refractivity, and reflectivity by using argon as the inert carrier gas is described. A semiconductor substrate is provided which may include semiconductor device structures. An Argon-based silicon-rich oxynitride etch stop layer is deposited overlying the semiconductor substrate. An oxide layer is deposited overlying the Argon-based silicon-rich oxynitride etch stop layer. An opening is etched through the oxide layer stopping at the Argon-based silicon-rich oxynitride etch stop layer. Thereafter, the Argon-based silicon-rich oxynitride etch stop layer within the opening is removed. The opening is filled with a conducting layer. This Argon-based silicon-rich oxynitride layer has improved uniformity across the wafer in terms of layer thickness, refractivity, and reflectivity as compared with a helium-based silicon-rich oxynitride layer.

Ar-based si-rich oxynitride film for dual damascene and/or contact etch stop layer

A method of forming an interconnect, comprising the following steps. A semiconductor structure is provided that has an exposed first metal contact and a dielectric layer formed thereover. An FSG layer having a predetermined thickness is then formed over the dielectric layer. A trench, having a predetermined width, is formed within the FSG layer and the dielectric layer exposing the first metal contact. A barrier layer, having a predetermined thickness, may be formed over the FSG layer and lining the trench side walls and bottom. A metal, preferably copper, is then deposited on the barrier layer to form a copper layer, having a predetermined thickness, over said barrier layer covered FSG layer, filling the lined trench and blanket filling the barrier layer covered FSG layer. The copper layer, and the barrier layer on said upper surface of said FSG layer, are planarized, exposing the upper surface of the FSG layer and forming a planarized copper filled trench. The FSG layer and planarized copper filled trench are then processed by either: (1) annealing from about 400 to 450.degree. C. for about one hour, then either NH.sub.3 or H.sub.2 plasma treating; or (2) Ar.sup.+ sputtering to ion implant Ar.sup.+ to a depth of less than about 300 .ANG. in the fluorinated silica glass layer, whereby any formed Si--OH bonds and copper oxide (metal oxide) are removed. A dielectric cap layer, having a predetermined thickness, is then formed over the processed FSG layer and the planarized copper filled trench.

Methods to improve copper-fluorinated silica glass interconnects

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Touten, Taiwan

Wen-Kung Cheng