Vanguard International Semiconductor Corporation

Wen-Jya Liang

Bin Liu

Chung-Ju Lee

Fu-Liang Yang

Ing-Ruey Liaw

Geeng-Lih Lin

Chao-Ming Koh

Yin-Pin Wang

Hung-Shern Tsai

Yeh-Sen Lin

Yuh-Sheng Chern

Jhy-Weei Hsia

Semiconductor devices for high voltage application are presented. A high power semiconductor device includes a first type doped semiconductor substrate and a second type doped epitaxial layer deposited thereon. A first type doped body region is disposed in the second type doped epitaxial layer. A heavily doped drain region is formed in the second type doped epitaxial layer and isolated from the first type doped body region with an isolation region and a channel. A second type deep heavily doped region extends from the heavily doped drain region to the semiconductor substrate. A pair of inversed type heavily doped source regions is disposed in the first type doped body region. A gate electrode is disposed overlying the channel with a dielectric layer interposed therebetween. The high power semiconductor device is isolated from the other semiconductor devices with a first type deep heavily doped region.

Semiconductor devices for high power application

A method for manufacturing a shallow trench isolation structure. A pad oxide layer and a mask layer are formed over a substrate. Portions of the mask layer, the pad layer and substrate are removed forming a trench. Oxidation of the substrate within the trench forms a linear oxide layer. The substrate at the bottom of the trench is exposed by removing a portion of the linear oxide layer at the bottom of the trench. A polysilicon layer, deposited completely over the mask, fills the trench as well. The polysilicon layer on the mask layer and outside the trench is removed, leaving polysilicon within the trench, which forms a polysilicon plug. A thin conformal barrier layer is formed over the substrate. An insulator layer is deposited above the barrier layer. The isolation layer and barrier layer on top of the mask as well as outside the trench are removed using a chemical mechanical polishing method. The mask is removed.

Method of forming shallow trench isolation structure

A conducting structure of a COB cell of DRAM includes an piecewise straight active area and substantially straight bitline formed over a semiconductor substrate upon which a first dielectric layer existed. Contact holes are formed over the piecewise straight active area for electrically exposing both nodes (source and drain), of the active area of the access device. An offset landing plug pattern is defined by a photoresist-clear pattern beside, say, the source node of the primary contact pattern and recess-etched into the first dielectric layer and electrically connected to the source node of the primary contact structure finally. The contact structure is then formed by a deposition-etched process, which performs as a landing plug for contact of the upper contact structures. The top area of the landing plug is defined through the additive pattern of the primary contact as well as the offset landing plug pattern. Thereafter, a second dielectric layer is deposited on the first dielectric layer and the contact structure. A bit line contact is then formed in the second dielectric layer and defined at the offset position of the source node of the landing plug contact structure and electrically connected with it, so as to provide a capability of forming a substantially straight bit line lies on an off-axis site to the piecewise straight active area and the primary substrate contact plug.

Fabrication method to approach the conducting structure of a DRAM cell with straightforward bit line

A method for manufacturing a stacked capacitor having fin-shaped electrodes with increased capacitance on a dynamic random access memory (DRAM) cell, was achieved. The invention eliminates the need for a silicon nitride etch stop layer, which is known to cause stress in the substrate and lead to defects. The capacitor bottom electrodes having fin shaped portions is fabricated by depositing a multilayer of alternate layers of silicon oxide and doped polysilicon on a partially completed DRAM device having FETs. After forming, with single masking step, the node contacts to the substrate in the multilayer and depositing another doped polysilicon layer, the polysilicon layers and oxide layer are patterned to form the electrodes. An important feature of this invention is that the patterned multilayer is etched to the silicon oxide layer over the bottom polysilicon layer and then the silicon oxide layer(s) are isotropically etched (e.g. in HF) to form the fin capacitor. The fin structure is then used as a mask to anisotropically etch the bottom polysilicon layer, and thereby complete and electrically isolate the bottom fin-shaped electrodes. The capacitor is completed by forming the inter-electrode dielectric and depositing a top electrode layer.

Method of manufacturing a stacked capacitor having a fin-shaped storage

This present invention is a method of fabricating a semiconductor memory cell in a DRAM. This invention utilizes a inter plug technique and nitride sidewall spacers to improve deep node contact etching damage and reduce the number of mask steps for typical landing pad processes. Thus, the method of this invention allows the manufacture of a semiconductor memory cell that reduces the difficulties due to the high aspect ratio of the contact hole of a storage node.

Growing community of inventors

Hsinchu, Taiwan

Wen-Jya Liang