Taiwan Semiconductor Manufacturing Comp. Ltd.

Wen-Hsin Wei

Hsien-Pin Hu

Shang-Yun Hou

Chen-Hua Douglas Yu

Chi-Hsi Wu

Ying-Ching Shih

Szu-Wei Lu

Tsung-Shu Lin

Tsung-Yu Chen

Jing-Cheng Lin

Wensen Hung

Chin-Fu Kao

Wei-Ming Chen

Wen-Chih Chiou

Hsing-Kuo Hsia

Sung-Hui Huang

Kuan-Yu Huang

Sao-Ling Chiu

Li-Chung Kuo

Ping-Kang Huang

Heh-Chang Huang

Chen-Hsiang Lao

Yushun Lin

Chih-Chieh Hung

Shih-Wen Huang

Chun Hua Chang

Tsung-Yang Hsieh

Chih-Ching Lin

Chih-Kai Cheng

Chun-Che Chen

Chih-Ta Shen

Jhih-Ming Lin

Wen-Jung Chuang

Shin-Puu Jeng

Li-Hui Cheng

Bruce C S Chou

Chih-Chien Pan

Weiming Chris Chen

Hsuan-Ning Shih

An integrated circuit package and a method of forming the same are provided. The method includes attaching an integrated circuit die to a first substrate. A dummy die is formed. The dummy die is attached to the first substrate adjacent the integrated circuit die. An encapsulant is formed over the first substrate and surrounding the dummy die and the integrated circuit die. The encapsulant, the dummy die and the integrated circuit die are planarized, a topmost surface of the encapsulant being substantially level with a topmost surface of the dummy die and a topmost surface of the integrated circuit die. An interior portion of the dummy die is removed. A remaining portion of the dummy die forms an annular structure.

Integrated circuit package and method of forming same

A semiconductor device includes a circuit substrate, a semiconductor package, and a metallic cover. The semiconductor package is disposed on the circuit substrate. The metallic cover is disposed over the semiconductor package and over the circuit substrate. The metallic cover comprises a cap and outer flanges. The cap overlies the semiconductor package. The outer flanges are disposed at edges of the cap, are connected with the cap, and extend towards the circuit substrate. A region of the bottom surface of the cap has a curved profile matching a warpage profile of the semiconductor package and the circuit substrate, and the region having the curved profile extends over the semiconductor package.

Semiconductor device having heat dissipation structure of curved profile and a manufacturing method thereof

An apparatus for manufacturing packaged semiconductor devices includes a lower plate having package platforms and clamp guide pins to align an upper plate with the lower plate, and a boat tray having windows configured to receive package devices, and a plurality of upper plates configured to be aligned to respective windows and respective package platforms. Clamping force can be applied by fasteners configured to generate a downward force upon the upper plate. Package devices on the platforms are thus subjected to a clamping force. Load cells measure the clamping force so adjustments can be made.

Package structure and method and equipment for forming the same

A semiconductor structure includes a first interposer; a second interposer laterally adjacent to the first interposer, where the second interposer is spaced apart from the first interposer; and a first die attached to a first side of the first interposer and attached to a first side of the second interposer, where the first side of the first interposer and the first side of the second interposer face the first die.

Giga interposer integration through Chip-On-Wafer-On-Substrate

A package structure and method for forming the same are provided. The package structure includes a first through via structure formed in a substrate and a semiconductor die formed below the first through via structure. The package structure further includes a conductive structure formed in a passivation layer over the substrate. The conductive structure includes a first via portion and a second via portion, the first via portion is directly over the first through via structure, and there is no conductive material directly below and in direct contact with the second via portion.

Package structure including through via structures

A packaged semiconductor device and a method and apparatus for forming the same are disclosed. In an embodiment, a method includes bonding a device die to a first surface of a substrate; depositing an adhesive on the first surface of the substrate; depositing a thermal interface material on a surface of the device die opposite the substrate; placing a lid over the device die and the substrate, the lid contacting the adhesive and the thermal interface material; applying a clamping force to the lid and the substrate; and while applying the clamping force, curing the adhesive and the thermal interface material.

Giga interposer integration through chip-on-wafer-on-substrate

An embodiment is a method including: attaching a first die to a first side of a first component using first electrical connectors, attaching a first side of a second die to first side of the first component using second electrical connectors, attaching a dummy die to the first side of the first component in a scribe line region of the first component, adhering a cover structure to a second side of the second die, and singulating the first component and the dummy die to form a package structure.

Package structures and methods of forming the same

A package structure includes a circuit substrate, a semiconductor package, a lid structure, a passive device and a barrier structure. The semiconductor package is disposed on and electrically connected to the circuit substrate. The lid structure is disposed on the circuit substrate covering the semiconductor package. The lid structure is attached to the circuit substrate through an adhesive material. The passive device is disposed on the circuit substrate in between the semiconductor package and the lid structure. The barrier structure is separating the passive device from the lid structure and the adhesive material, and the barrier structure is in contact with the adhesive material.

Package structure and method of fabricating the same

An interposer substrate is manufactured with a scribe line between adjacent regions. In an embodiment a separate exposure reticle is utilized to pattern the scribe line. The exposure reticle to pattern the scribe line will create an exposure region which overlaps and overhangs the exposure regions utilized to form adjacent regions.

Semiconductor device and method of manufacture

Method of forming a dummy die of an integrated circuit having an embedded annular structure

A package structure includes a first through via structure formed in a substrate and a semiconductor die formed below the first through via structure. The package structure further includes a conductive structure formed in a passivation layer over the substrate. The conductive structure includes a first via portion and a second via portion, the first via portion is directly over the first through via structure, and there is no conductive material directly below and in direct contact with the second via portion.

Package structure having line connected via portions

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Hsinchu, Taiwan

Wen-Hsin Wei