Taiwan Semiconductor Manufacturing Comp. Ltd.

Other

Mediatek Corporation

Haynes and Boone, Llp

Wen-Chun Huang

Ru-Gun Liu

Ming-Hui Chih

Hung-Chun Wang

Tsai-Sheng Gau

Chih-Ming Lai

Tsong-Hua Ou

Chia-Ping Chiang

Wen-Li Cheng

Cheng Kun Tsai

Ken-Hsien Hsieh

Ping-Chieh Wu

Yu-Po Tang

Boren Luo

Nian-Fuh Cheng

Wen-Hao Liu

Ching-Hsu Chang

Ying-Chou Cheng

Tzu-Chin Lin

Chih-Wei Hsu

Jeng-Horng Chen

Feng-Ju Chang

Chun-Hung Wu

Cheng-Lung Tsai

Cheng-Kun Tsai

Ya-Ting Chang

Yao-Ching Ku

Tsung-Yu Wang

Shih-Ming Chang

Wei-Chen Chien

Hui En Yin

Chi-Ping Liu

Kuei Shun Chen

Chih-Shiang Chou

Pei-Shiang Chen

Burn Jeng Lin

Wen-Ju Preet Yang

Chii-Ping Chen

Te-Chih Huang

Chih-Yang Yeh

Cliff Hou

Pi-Tsung Chen

Yu Lun Liu

Feng-Lung Lin

Faruk Krecinic

Lee-Chung Lu

Dian-Hau Chen

Shy-Jay Lin

Ming-Feng Shieh

Yung-Sung Yen

Huang-Yu Chen

Hsien-Cheng Wang

Ming-Chang Wen

Gwan Sin Chang

Chien-Hsun Chen

Cheng-Cheng Kuo

George Liu

Chen-Yu Chen

Shih-Che Wang

Jiing-Feng Yang

Hung Chang Hsieh

Wei-Chao Chiu

Jing-Cheng Lin

Li-Chun Tien

Hsin-Chang Lee

Yi-Kan Cheng

Wen-Hao Chen

Yuan-Te Hou

Chi-Cheng Hung

Wen-Sung Hsu

Hua-Tai Lin

Chin-Chang Hsu

Hsi-Kuei Cheng

Kuo-Chio Liu

Ke-Ying Su

Chia-Chu Liu

Chih-Hsien Lin

Cheng-I Huang

Hsiao-Shu Chao

Cheng-Hung Chen

Hsu-Ting Huang

Hsiang-Tai Lu

Chi-Yuan Chen

Kuei-Liang Lu

Ko-Bin Kao

Chien-Chen Li

Cheng-Hung Yeh

Dong-Hsu Cheng

Nien-Yu Tsai

Ruey-Yun Shiue

Chia-Chi Lin

Hsien-Huang Liao

Fang-Yu Fan

Jia-Guei Jou

Shih-Chi Wang

Chih-Chung Huang

Yao-Pang Hsu

Tzu-Chun Lo

Ching-Che Tsai

Tzi-Yi Shieh

The present disclosure provides a method of patterning a target material layer over a semiconductor substrate. The method includes steps of forming a spacer feature over the target material layer using a first sub-layout and performing a photolithographic patterning process using a second sub-layout to form a first feature. A portion of the first feature extends over the spacer feature. The method further includes steps of removing the portion of the first feature extending over the spacer feature and removing the spacer feature. Other methods and associated patterned semiconductor wafers are also provided herein.

Methods for integrated circuit design and fabrication

Implementations of the present disclosure provide coloring methods that sort and pre-color nodes of G0-linked networks in a multiple-patterning technology (MPT)-compliant layout design by coordinate. In one embodiment, a method includes identifying target networks in a circuit layout, each target network having two or more linked nodes representing circuit patterns, and each target network being presented in an imaginary X-Y coordinate plane, assigning a first feature to a first node in each target network, the first node is determined using a coordinate-based method, and assigning the first feature and a second feature to remaining nodes in each target network in an alternating manner so that any two immediately adjacent linked nodes in each target network have different features.

Method for coloring circuit layout and system for performing the same

A semiconductor package includes a substrate having a top surface and a bottom surface; a semiconductor die mounted on the top surface of the substrate; and a two-part lid mounted on a perimeter of the top surface of the substrate and housing the semiconductor die. The lid comprises an annular lid base and a cover plate removably installed on the annular lid base. The semiconductor package can be uncovered by removing the cover plate and a forced cooling module can be installed in place of the cover plate.

Lidded semiconductor package

Implementations of the disclosure provide a method of fabricating an integrated circuit (IC). The method includes receiving an IC design layout; performing optical proximity correction (OPC) process to the IC design layout to produce a corrected IC design layout; and verifying the corrected IC design layout using a machine learning algorithm. The post OPC verification includes using the machine learning algorithm to identify one or more features of the corrected IC design layout; comparing the one or more identified features to a database comprising a plurality of features; and verifying the corrected IC design layout based on labels in the database associated with the plurality of features.

Method of post optical proximity correction (OPC) printing verification by machine learning

Optical proximity correction (OPC) based computational lithography techniques are disclosed herein for enhancing lithography printability. An exemplary mask optimization method includes receiving an integrated circuit (IC) design layout having an IC pattern; generating target points for a contour corresponding with the IC pattern based on a target placement model, wherein the target placement model is selected based on a classification of the IC pattern; and performing an OPC on the IC pattern using the target points, thereby generating a modified IC design layout. The method can further include fabricating a mask based on the modified IC design layout. The OPC can select an OPC model based on the classification of the IC pattern. The OPC model can weight the target placement model.

Optical proximity correction methodology using pattern classification for target placement

The present disclosure relates to a method of data preparation. The method, in some embodiments, performs a first data preparation process using a data preparation element. The first data preparation process modifies a plurality of shapes of an integrated chip (IC) design that comprises a graphical representation of a layout used to fabricate an integrated chip. A plurality of additional shapes are added to the IC design using an additional shape insertion element. The plurality of additional shapes are separated from the plurality of shapes by one or more non-zero distances. A second data preparation process is performed using the data preparation element, after performing the first data preparation process. The second data preparation process modifies the plurality of additional shapes.

Methodology for pattern density optimization

Disclosed is a method of fabricating an integrated circuit (IC) using a multiple (N&#x3e;2) patterning technique. The method provides a layout of the IC having a set of IC features. The method further includes deriving a graph from the layout, the graph having vertices connected by edges, the vertices representing the IC features, and the edges representing spacing between the IC features. The method further includes selecting vertices, wherein the selected vertices are not directly connected by an edge, and share at least one neighboring vertex that is connected by N edges. The method further includes using a computerized IC tool to merge the selected vertices, thereby reducing a number of edges connecting the neighboring vertex to be below N. The method further includes removing a portion of the vertices that are connected by less than N edges.

Multiple patterning method for semiconductor devices

An integrated circuit (IC) manufacturing method includes receiving an IC design layout having IC regions separate from each other. Each of the IC regions includes an initial IC pattern that is substantially identical among the IC regions. The method further includes identifying a group of IC regions from the IC regions. All IC regions in the group have a substantially same location effect, which is introduced by global locations of the IC regions on the IC design layout. The method further includes performing a correction process to a first IC region in the group, modifying the initial IC pattern in the first IC region into a first corrected IC pattern. The correction process includes using a computer program to correct location effect. The method further includes replacing the initial IC pattern in a second IC region in the group with the first corrected IC pattern.

Method for integrated circuit manufacturing

Examples of optical proximity correction (OPC) based computational lithography techniques are disclosed herein. An exemplary method includes receiving an IC design layout that includes an IC feature, the IC feature specifying a mask feature for selectively exposing to radiation a portion of a photoresist disposed on a substrate; determining topographical information of an underlying layer disposed on the substrate between the photoresist and the substrate; performing an OPC process on the IC feature to generate a modified IC feature; and providing a modified IC design layout including the modified IC feature for fabricating a mask based on the modified IC design layout. The OPC process may use the topographical information of the underlying layer to compensate for an amount of radiation directed towards the portion of the photoresist so as to expose the portion of the photoresist to a target dosage of radiation.

Optical proximity correction methodology using underlying layer information

Growing community of inventors

Tainan, Taiwan

Wen-Chun Huang