Taiwan Semiconductor Manufacturing Comp. Ltd.

E Ink Holdings Inc.

Wen-Chuan Wang

Shy-Jay Lin

Burn Jeng Lin

Jaw-Jung Shin

Pei-Yi Liu

Shih-Ming Chang

Chi-Lun Lu

Cheng-Hung Chen

Sheng-Chi Chin

Jyuh-Fuh Lin

Chin-Hsiang Lin

Chih-Cheng Chin

Chang-Cheng Hung

Chung-Hsing Chang

Yen-Bin Huang

Anthony Yen

Shinn-Sheng Yu

Cheng-Chi Wu

Chen-Yuan Hsia

Ching-Yu Chang

Chun-Kuang Chen

Hung-Chang Hsieh

Ting-Hao Hsu

Ching-Fang Yu

Hung Chang Hsieh

Hsin-Chang Lee

Heng-Hsin Liu

Tsai-Sheng Gau

Chia-Jen Chen

Chih-Ming Ke

Ian French

Te-Chih Huang

Kuang-Heng Liang

Jan-Wen You

Wei-Yu Su

Tyng-Hao Hsu

Chih-Ching Wang

Hong-Chang Hsieh

Jensen Yang

Allen Hsia

Kai-Chung Liu

Chih-Chen Chin

An extreme ultraviolet lithography method is disclosed. In an example, the EUVL method includes forming a resist layer on a substrate; performing a first exposure process to image a first pattern of a first sub-region of a first mask to the resist layer; performing a second exposure process to image a second pattern of a second sub-region of the first mask to the resist layer; and performing a third exposure process to image a third pattern of a first sub-region of a second mask to the resist layer. The second and third patterns are identical to the first pattern. The first, second and third exposure processes collectively form a latent image of the first pattern on the resist layer.

Lithography method with reduced impacts of mask defects

A display device including a display panel and a driving circuit is provided. The display panel is configured to display an image frame. The driving circuit is coupled to the display panel. The driving circuit is configured to output a gate signal to drive the display panel to display the image frame during a driving period. The driving period includes a first period, a second period, and a third period. The gate signal has a first voltage level during the first period and a second voltage level during the second period. The second voltage level is greater than the first voltage level.

Display device and driving method thereof

A method includes obtaining a layout of a circuit pattern implemented on a semiconductor wafer, and identifying one or more polygons in the layout based on a length criteria. One or more measurement gauges are placed on the identified polygons to thereby obtain measured polygons. A scanning electron microscope (SEM) image of the circuit pattern is obtained. The SEM image is aligned with the layout including the measured polygons. A critical dimension of one or more objects in the SEM image is measured. The one or more objects correspond to the one or more polygons. Based on the measured critical dimension, it is determined whether the circuit pattern is acceptable.

Wafer-to-design image analysis (WDIA) system

The present disclosure provides one embodiment of an IC method that includes receiving an IC design layout, which has a plurality of main features and a plurality of space blocks. The IC method also includes calculating an optimized block dummy density ratio rto optimize a uniformity of pattern density (UPD), determining a target block dummy density ratio R, determining size, pitch and type of a non-printable dummy feature, generating a pattern for dummy features and adding the dummy features in the IC design layout.

Method of fabricating an integrated circuit with non-printable dummy features

The present disclosure provides one embodiment of an IC method. First pattern densities (PDs) of a plurality of templates of an IC design layout are received. Then a high PD outlier template and a low PD outlier template from the plurality of templates are identified. The high PD outlier template is split into multiple subsets of template and each subset of template carries a portion of PD of the high PD outlier template. A PD uniformity (PDU) optimization is performed to the low PD outlier template and multiple individual exposure processes are applied by using respective subset of templates.

Method of fabricating an integrated circuit with a pattern density-outlier-treatment for optimized pattern density uniformity

Disclosed is a lithography system. The lithography system includes a radiation source to provide radiation energy for lithography exposure; a substrate stage configured to secure a substrate; an imaging lens module configured to direct the radiation energy onto the substrate; at least one sensor configured to detect a radiation signal directed from the substrate; and a pattern extraction module coupled with the at least one sensor and designed to extract a pattern of the substrate based on the radiation signal.

System and method for real-time overlay error reduction

A method includes inspecting a mask to locate a defect region for a defect of the mask. A phase distribution of an aerial image of the defect region is acquired. A point spread function of an imaging system is determined. One or more repair regions of the mask are identified based on the phase distribution of the aerial image of the defect region and the point spread function. A repair process is performed to the one or more repair regions of the mask to form one or more repair features.

Method for repairing a mask

The present disclosure provides a lithography system comprising a radiation source and an exposure tool including a plurality of exposure columns densely packed in a first direction. Each exposure column includes an exposure area configured to pass the radiation source. The system also includes a wafer carrier configured to secure and move one or more wafers along a second direction that is perpendicular to the first direction, so that the one or more wafers are exposed by the exposure tool to form patterns along the second direction. The one or more wafers are covered with resist layer and aligned in the second direction on the wafer carrier.

Systems and methods for high-throughput and small-footprint scanning exposure for lithography

A system and method for maskless direct write lithography are disclosed. The method includes receiving a plurality of pixels that represent an integrated circuit (IC) layout; identifying a first subset of the pixels that are suitable for a first compression method; and identifying a second subset of the pixels that are suitable for a second compression method. The method further includes compressing the first and second subset using the first and second compression method respectively, resulting in compressed data. The method further includes delivering the compressed data to a maskless direct writer for manufacturing a substrate. In embodiments, the first compression method uses a run-length encoding and the second compression method uses a dictionary-based encoding. Due to the hybrid compression method, the compressed data can be decompressed with a data rate expansion ratio sufficient for high-volume IC manufacturing.

System and method for maskless direct write lithography

Lithography methods disclosed herein accommodate shrinking pattern dimensions. An exemplary method includes receiving a pattern to be transferred to a workpiece by a pattern generator. The pattern generator is divided into a first segment set and a second segment set based on the pattern, such that a collective exposure dose from the first segment set and the second segment set satisfies an exposure dose specified by the pattern. The first segment set is offset from the second segment set in a first direction, and segments in the first segment set and segments in the second segment set are offset from each other in a second direction different than the first direction. The method further includes exposing the workpiece according to the first segment set and the second segment set.

Grid refinement method

A technique for converting design shapes into pixel values is provided. The technique may be used to control a direct-write or other lithographic process performed on a workpiece. In an exemplary embodiment, the method includes receiving, at a computing system, a design database specifying a feature having more than four vertices. The computing system also receives a pixel grid. A set of rectangles corresponding to the feature is determined, and the computing system determines an area of a pixel of the pixel grid overlapped by the feature based on the set of rectangles. In some such embodiments, a lithographic exposure intensity is determined for the pixel based on the area overlapped by the feature, and the lithographic exposure intensity is provided for patterning of a workpiece.

System and technique for rasterizing circuit layout data

Growing community of inventors

Hsinchu, Taiwan

Wen-Chuan Wang