Fujitsu Corporation

Altera Corporation

Other

Wen-chou Vincent Wang

Solomon I Beilin

William T Chou

Michael G Lee

Michael G Peters

James J Roman

Larry Louis Moresco

Tetsuzo Yoshimura

David Kudzuma

Masaaki Inao

Yuan Hang Li

Yasuhito Takahashi

Thomas Joel Massingill

David A Horine

Som S Swamy

Yashuhito Takahashi

Mark Thomas McCormack

Richard L Wheeler

Teruo Murase

Vadali Mahadev

Bruce Euzent

David G Love

Donald S Fritz

Lei Zhang

Hunt Hang Jiang

Bidyut Kanti Sen

Dashun Steve Zhou

Kiyoshi Kuwabara

Vivek Mansingh

Connie M Wong

Patricia R Boucher

Don Fritz

Habib Vafi

Provided are semiconductor die flip chip packages and semiconductor die flip chip package components where certain properties of the packages/components are controlled to facilitate management of the package stresses. Also provided are fabrication methods for such packages and package components. For instance, the thickness of a die can be controlled such that the stress generated/experienced by the die is minimized. As such, the package stress is managed to suitable levels for incorporation of a low-K Si die and/or a thin package substrate. Further, a thin die can be attached to a heat spreader to increase the rigidity for easier handling during fabrication of the semiconductor die flip chip package.

Structure and assembly procedure for low stress thin die flip chip packages designed for low-K Si and thin core substrate

Multi-layered, organic build-up semiconductor package substrates have build-up layers with layers of both fibrous organic dielectric material and non-fibrous organic dielectric material. Non-fibrous dielectric material layers are positioned below the signal metal layers and fibrous dielectric material layers are positioned below the power/ground plane metal layers. The package substrate combines in a single package substrate the advantages of rigidity, strength and relatively low CTE of a fibrous material with the capacity of a non-fibrous material to achieve fine resolution signal metal lines.

Package substrate with dual material build-up layers

Provided are semiconductor low-K Si die wire bonding packages with package stress control and fabrication methods for such packages. The packages include molding interface material applied onto the low-K Si die. In general, the molding interface material is selectively applied onto the low-K Si die surface in order to minimize to safe levels the package stress experienced by the low-K Si die. Selective application includes defining various combinatorial patterns of coated and non-coated regions. In addition, selective application may also include a general application of molding interface material to create a stress buffer zone. The results are packages with less stress experienced by the low-K Si die and so improved reliability (in compliance with industry specifications).

Structure, material, and design for assembling a low-K Si die to achieve an industrial grade reliability wire bonding package

The present invention is directed to a new bonding pad structure that includes a copper pad and a pad surface finish comprising multiple layers of solder. The multiple layers of solder include at least a layer of eutectic solder (or a layer of pure-Sn solder) covering the copper pad and a layer of high-Pb solder covering the layer of eutectic solder (or the layer of pure-Sn solder). Since the layer of high-Pb solder is significantly thicker than the eutectic solder layer (or the layer of pure-Sn solder), there is insufficient tin supply in the eutectic solder (or the layer of pure-Sn solder) for forming a thick Cu/Sn intermetallic layer on the copper pad. Instead, a thin Cu/Sn intermetallic layer is formed on the copper pad and there is less likelihood of forming a crack in the thin Cu/Sn intermetallic layer.

Pad surface finish for high routing density substrate of BGA packages

Provided are a semiconductor low-K Si die flip chip package with warpage control and fabrication methods for such packages. The packages include heat spreaders that are attached to the low-K Si die and packaging substrate. In general, the modulus of the thermal interface material, which is used to attach the heat spreader to the low-K Si die, is selected as high as possible relative to other commercially available thermal interface materials. On the other hand, the modulus of the adhesive, which is used to attach the heat spreader via an optional stiffener to the substrate, is selected as low as possible relative to other commercially available adhesives. The result is a package with less bowing and so improved co-planarity (in compliance with industry specifications) with the surface to which it is ultimately bound. Moreover, the low-K Si die and package reliabilities are thereby enhanced.

Structure and material for assembling a low-K Si die to achieve a low warpage and industrial grade reliability flip chip package with organic substrate

Provided are a semiconductor flip chip package with warpage control and fabrication methods for such packages. The packages of the present invention include heat spreader lids that are rigidly attached to the die or packaging substrate with a bond that can withstand the considerable bowing pressures caused by the CTE mismatch between the die and substrate. The result is a package with less bowing and so improved co-planarity (in compliance with industry specifications) with the PCB board to which it is ultimately bound. Package reliability is thereby also enhanced, particularly for large die sizes.

Flip chip package with warpage control

A method for deplating defective capacitors comprising forming a plurality of capacitors on a semiconductor substrate, forming a plurality of metal contacts on the plurality of capacitors, and depositing a layer of photoresist on the semiconductor substrate. The photoresist layer is patterned so that the plurality of metal contacts are exposed, which are then contacted with an electrically conductive solution. The metal contacts, which are disposed over defective capacitors, are subsequently deplated. A method for forming a multi-chip module comprising forming a thin-film polymeric interconnect structure having a pair of sides, one of which is disposed on a silicon substrate having active or passive devices and the other of which has a computer chip mounted thereon. A multi-chip module formed by the method.

Multi-chip module and method for forming and method for deplating defective capacitors

Opto-electrical systems having electrical and optical interconnections formed in thin layers are disclosed. In one set of preferred embodiments, optical signals are conveyed between layers by respective vertical optical couplers disposed on the layers. In other preferred embodiments, optical signals are conveyed by stack optical waveguide coupling means. Yet other preferred embodiments have electrical via means formed in one or more layers to covey electrical signals between two or more layers.

Multi-layer opto-electronic substrates with electrical and optical interconnections and methods for making

An optoreflective structure for reflecting an optical signal following a path defined by an optical waveguide comprising a first cladding layer having a first planar cladding surface; a waveguide disposed on the first cladding layer; and a second cladding layer disposed on the waveguide and having a second planar cladding surface. The first cladding layer, the second cladding layer and the waveguide terminate in a generally dove-tailed structure having a beveled planar surface. An optoreflector is disposed on the beveled planar surface for a changing direction of an optical signal passing through the waveguide. Methods of producing the optoreflective structure are disclosed.

Single and multilayer waveguides and fabrication process

Provided are flip chip device assembly methods that integrate the solder joining and underfill operations of the assembly process. Solder joining of the die and substrate and curing of the underfill material between the die and substrate is accomplished in the same heating and cooling operation. As a result, the coefficient of thermal expansion (CTE) mismatch stresses incurred prior to application and curing of underfill by a device packaged according to the conventional technique having a separate heating and cooling operation following solder joining, are avoided. These stresses are of particular concern in smaller device size technologies (e.g., 0.13 microns and smaller) using low k dielectrics and large die sizes due the difference in CTP between the die and substrate.

Integrated assembly-underfill flip chip process

Methods of planarizing structures formed on the surfaces of substrates and wafers are disclosed. The methods form a planarizing layer over the surface and the structures, or the locations where the structures are to be formed, such that the top surface of the layer has low areas between the locations of the structures, and such that the low areas lie substantially within a plane which is below the tops of the structures. A polish-stop layer is thee formed over the low areas of the planarizing layer, the polish-stop layer being more resistant to polishing than the planarizing layer and, preferably, the structures. The resulting surface is then polished. The polishing may be accomplished by, for example, standard mechanical polishing, and chemical-mechanical polishing.

Methods of planarizing structures on wafers and substrates by polishing

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Cupertino, CA, United States of America

Wen-chou Vincent Wang