Taiwan Semiconductor Manufacturing Comp. Ltd.

TSMC Solid State Lighting Ltd.

Epistar Corporation

National Science Council

Wen-Chih Chiou

Chen-Hua Douglas Yu

Tsang-Jiuh Wu

Ku-Feng Yang

Weng-Jin Wu

Yung-Chi Lin

Shin-Puu Jeng

Ding-Yuan Chen

Jing-Cheng Lin

Hsin-Yu Chen

Chia-Lin Yu

Yi-Hsiu Chen

Hung-Jung Tu

Hung-Pin Chang

Shang-Yun Hou

Ming-Fa Chen

Ebin Liao

Ming-Tsu Chung

Chen-Yu Tsai

Fang Wen Tsai

Lin-Chih Huang

Der-Chyang Yeh

Ying-Ching Shih

Hung-Ta Lin

Shau-Lin Shue

Syun-Ming Jang Jang

Ying-Ho Chen

Chun Hua Chang

Chi-Hsi Wu

Tsu Shih

Yuan-Hung Liu

Yu-Liang Lin

An-Jhih Su

Hsien-Pin Hu

Sung-Feng Yeh

Hsien-Wei Chen

Li-Hsien Huang

Cheng-Hung Chang

Sao-Ling Chiu

Ping-Kang Huang

Hsin Chang

Szu-Wei Lu

Ming Shih Yeh

Kuang-Wei Cheng

Wei-Cheng Wu

Jui-Pin Hung

Chia-Hao Hsu

Bruce C S Chou

Jean Wang

Fang-Cheng Chen

Chung-Shi Liu

Chen-Shien Chen

Po-Hao Tsai

Cheng-Lin Huang

Kuo-Ching Hsu

Wen-Ching Tsai

Wen-Hsin Wei

Shih Ting Lin

Tu-Hao Yu

Tien-I Bao

Hai-Ching Chen

Keng-Chu Lin

Tsung-Ding Wang

Yu-Sheng Lin

Liang-Guang Chen

Shing-Chyang Pan

Li-Han Hsu

Chiung-Han Yeh

Shwang-Ming Jeng

Hsiang-Fan Lee

Hsin-Hsien Lu

Shih-Peng Tai

Jun-Lin Yeh

Tzu-Yu Wang

Chia-Ho Chen

Yen-Ming Chen

Ying-Ju Chen

Yung-Cheng Lu

Hun-Jan Tao

Ching-Wen Hsiao

Han-Ping Pu

Jyu-Horng Shieh

Li-Hui Cheng

Chen-Cheng Kuo

Hung-Wen Su

Chih-Wei Wu

Chia-Jen Chen

Chin-Fu Kao

Kuo-Chiang Ting

Hsien-Ming Lee

Pu Wang

Kai-Ming Ching

Chih-Hsien Lin

Chih-Hao Chen

Peng-Fu Hsu

William Weilun Hong

Baw-Ching Perng

Weiming Chris Chen

Kewei Zuo

Francis Ko

A semiconductor device and a method of forming the same are provided. The semiconductor device includes a first logic die including a first through via, an image sensor die hybrid bonded to the first logic die, and a second logic die bonded to the first logic die. A front side of the first logic die facing a front side of the image sensor die. A front side of the second logic die facing a backside of the first logic die. The second logic die comprising a first conductive pad electrically coupled to the first through via.

Stacked image sensor device and method of forming same

A semiconductor device and method of manufacture are provided wherein the semiconductor device includes a first system on chip device bonded to a first memory device, a second system on chip device bonded to the first memory device, a first encapsulant surrounding the first system on chip device and the second system on chip device, a second encapsulant surrounding the first system on chip device, the second system on chip device, and the first memory device, and a through via extending from a first side of the second encapsulant to a second side of the first encapsulant, the through via being located outside of the first encapsulant.

Method of manufacturing semiconductor devices with system on chip devices

A semiconductor device includes a substrate, a package structure, a thermal interface material (TIM) structure, and a lid structure. The package structure is disposed on the substrate. The TIM structure is disposed on the package structure. The TIM structure includes a metallic TIM layer and a non-metallic TIM layer in contact with the metallic TIM layer, and the non-metallic TIM layer surrounds the metallic TIM layer. The lid structure is disposed on the substrate and the TIM structure.

Semiconductor device and manufacturing method thereof

In an embodiment, a device includes: an interposer; a first integrated circuit device bonded to the interposer with dielectric-to-dielectric bonds and with metal-to-metal bonds; a second integrated circuit device bonded to the interposer with dielectric-to-dielectric bonds and with metal-to-metal bonds; a buffer layer around the first integrated circuit device and the second integrated circuit device, the buffer layer including a stress reduction material having a first Young's modulus; and an encapsulant around the buffer layer, the first integrated circuit device, and the second integrated circuit device, the encapsulant including a molding material having a second Young's modulus, the first Young's modulus less than the second Young's modulus.

Integrated circuit package and method

An embodiment bonded integrated circuit (IC) structure includes a first IC structure and a second IC structure bonded to the first IC structure. The first IC structure includes a first bonding layer and a connector. The second IC structure includes a second bonding layer bonded to and contacting the first bonding layer and a contact pad in the second bonding layer. The connector extends past an interface between the first bonding layer and the second bonding layer, and the contact pad contacts a lateral surface and a sidewall of the connector.

3D integrated circuit (3DIC) structure

A method includes attaching a wafer to a wafer chuck having a curved surface. The method further includes placing a device die on the wafer, such that a first dielectric layer of the device die is in contact with a second dielectric layer of the wafer, and performing an annealing process to bond the first dielectric layer to the second dielectric layer. The method further includes encapsulating the device die with an encapsulating material, forming redistribution lines overlapping the encapsulating material and the device die, and sawing the encapsulating material to form a plurality of packages.

Method of forming package structure by using a wafer chuck with adjustable curved surface

In an embodiment, a device includes: a first wafer including a first substrate and a first interconnect structure, a sidewall of the first interconnect structure forming an obtuse angle with a sidewall of the first substrate; and a second wafer bonded to the first wafer, the second wafer including a second substrate and a second interconnect structure, the sidewall of the first substrate being laterally offset from a sidewall of the second substrate and a sidewall of the second interconnect structure.

Wafer bonding method

A semiconductor apparatus for pre-wetting a semiconductor workpiece includes a process chamber, a workpiece holder disposed within the process chamber to hold the semiconductor workpiece, a pre-wetting fluid tank disposed outside the process chamber and containing a pre-wetting fluid, and a conduit coupled to the pre-wetting fluid tank and extending into the process chamber. The conduit delivers the pre-wetting fluid from the pre-wetting fluid tank out through an outlet of the conduit to wet a major surface of the semiconductor workpiece, wherein the outlet of the conduit is positioned above the major surface of the semiconductor workpiece by a vertical distance.

Apparatus and method for wafer pre-wetting

A method includes putting a first package component into contact with a second package component. The first package component comprises a first dielectric layer including a first dielectric material, and the first dielectric material is a silicon-oxide-based dielectric material. The second package component includes a second dielectric layer including a second dielectric material different from the first dielectric material. The second dielectric material comprises silicon and an element selected from the group consisting of carbon, nitrogen, and combinations thereof. An annealing process is performed to bond the first dielectric layer to the second dielectric layer.

Heterogeneous dielectric bonding scheme

A package structure including a semiconductor die, a redistribution circuit structure, a backside dielectric layer, conductive terminals, an electronic device, and an underfill is provided. The semiconductor die laterally encapsulated by an insulating encapsulation. The redistribution circuit structure is disposed on the semiconductor die and the insulating encapsulation. The redistribution circuit structure includes redistribution conductive layers and thermal enhancement structures electrically insulated from the redistribution conductive layers, and the thermal enhancement structures are thermally coupled to the semiconductor die. The backside dielectric layer is disposed on the redistribution circuit structure. The conductive terminals penetrate through the backside dielectric layer. The electronic device is disposed over the backside dielectric layer and electrically connected to the redistribution circuit structure through the conductive terminals. The underfill is disposed between the backside dielectric layer and the electronic device, wherein the underfill is thermally coupled to the thermal enhancement structures.

Package structure

A semiconductor device includes a through-substrate via extending from a frontside to a backside of a semiconductor substrate. The through-substrate via includes a concave or a convex portion adjacent to the backside of the semiconductor substrate. An isolation film is formed on the backside of the semiconductor substrate. A conductive layer includes a first portion formed on the concave or convex portion of the through substrate via and a second portion formed on the isolation film. A passivation layer partially covers the conductive layer.

Semiconductor device having backside interconnect structure on through substrate via

A semiconductor device includes a photonic die and an optical die. The photonic die includes a grating coupler and an optical device. The optical device is connected to the grating coupler to receive radiation of predetermined wavelength incident on the grating coupler. The optical die is disposed over the photonic die and includes a substrate with optical nanostructures. Positions and shapes of the optical nanostructures are such to perform an optical transformation on the incident radiation of predetermined wavelength when the incident radiation passes through an area of the substrate where the optical nanostructures are located. The optical nanostructures overlie the grating coupler so that the incident radiation of predetermined wavelength crosses the optical die where the optical nanostructures are located before reaching the grating coupler.

Semiconductor device and manufacturing method thereof having grating coupled dies and nanostructures

A semiconductor structure including a first die, a second die stacked on the first die, a smoothing layer disposed on the first die and a filling material layer disposed on the smoothing layer. The second die has a dielectric portion and a semiconductor material portion disposed on the dielectric portion. The smoothing layer includes a first dielectric layer and a second dielectric layer, and the second dielectric layer is disposed on the first dielectric layer. The dielectric portion is surrounded by the smoothing layer, and the semiconductor material portion is surrounded by the filling material layer. A material of the first dielectric layer is different from a material of the second dielectric layer and a material of the filling material layer.

Semiconductor structure and manufacturing method thereof

Provided are integrated circuit packages and methods of forming the same. An integrated circuit package includes at least one first die, a plurality of bumps, a second die and a dielectric layer. The bumps are electrically connected to the at least one first die at a first side of the at least one first die. The second die is electrically connected to the at least one first die at a second side of the at least one first die. The second side is opposite to the first side of the at least one first die. The dielectric layer is disposed between the at least one first die and the second die and covers a sidewall of the at least one first die.

Integrated circuit packages

A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes an interconnect structure disposed over a semiconductor substrate, contact pads disposed on the interconnect structure, a dielectric structure disposed on the interconnect structure and covering the contact pads, bonding connectors covered by the dielectric structure and landing on the contact pads, and a dummy feature covered by the dielectric structure and laterally interposed between adjacent two of the bonding connectors. Top surfaces of the bonding connectors are substantially coplanar with a top surface of the dielectric structure, and the bonding connectors are electrically coupled to the interconnect structure through the contact pads.

Semiconductor structure comprising dummy feature interposed between the bonding connectors

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Miaoli, Taiwan

Wen-Chih Chiou