Freescale Semiconductor,inc.

Nxp USA, Inc.

Weixiao Huang

Ronghua Zhu

Vishnu Khemka

Jenn Hwa Huang

Tahir Arif Khan

Bernhard Grote

Bruce McRae Green

A low leakage current switch device () is provided which includes a GaN-on-Si substrate () with one or more device mesas () in which isolation regions () are formed using an implant mask () to implant ions () into an upper portion of the mesa sidewalls and the peripheral region around each elevated surface of the mesa structures exposed by the implant mask, thereby preventing the subsequently formed gate electrode () from contacting the peripheral edge and sidewalls of the mesa structures.

GaN-on-Si switch devices

In some embodiments, a metal insulator semiconductor heterostructure field effect transistor (MISHFET) is disclosed that has a source, a drain, an insulation layer, a gate dielectric, and a gate. The source and drain are on opposing sides of a channel region of a channel layer. The channel region is an upper portion of the channel layer. The channel layer comprises gallium nitride. The insulation layer is over the channel layer and has a first portion and a second portion. The first portion is nearer the drain than the source and has a first thickness. The second portion is nearer the source than drain and has the first thickness. The insulation layer has an opening through the insulation layer. The opening is between the first portion and the second portion.

Semiconductor device and method of making

Transistors () employing floating buried layers may be susceptible to noise coupling into the floating buried layers. In IGFETS this is reduced or eliminated by providing a normally-ON switch () coupling the buried layer () and the IGFET source () or drain (). When the transistor () is OFF, this clamps the buried layer voltage and substantially prevents noise coupling thereto. When the drain-source voltage Vexceeds the switch's () threshold voltage Vt, it turns OFF, allowing the buried layer () to float, and thereby resume normal transistor action without degrading the breakdown voltage or ON-resistance. In a preferred embodiment, a normally-ON lateral JFET (---) conveniently provides this switching function. The lateral JFET (-) can be included in the device () by mask changes without adding or customizing any process steps, thereby providing the improved noise resistance without significant increase in manufacturing cost. The improvement applies to both P (-) and N channel (---) transistors and is particularly useful for LDMOS devices.

Semiconductor device and method

Transistors () employing floating buried layers (BL) () may exhibit transient breakdown voltage (BVdss)significantly less than (BVdss). It is found that this occurs because the floating BL () fails to rapidly follow the applied transient, causing the local electric field within the device to temporarily exceed avalanche conditions. (BVdss)of such transistors () can be improved to equal or exceed (BVdss)by including a charge pump capacitance () coupling the floating BL () to whichever high-side terminal () receives the transient. The charge pump capacitance () may be external to the transistor (), may be formed on the device surface () or, may be formed internally to the transistor (--) using a dielectric deep trench isolation wall () separating DC isolated sinker regions () extending to the BL (). The improvement is particularly useful for LDMOS devices.

Electronic device with capcitively coupled floating buried layer

Methods and apparatus are provided for fabricating a semiconductor device structure. The semiconductor device structure comprises a buried region having a first conductivity type, a first region having a second conductivity type overlying the buried region, a source region having the first conductivity type overlying the first region, and a drain region having the first conductivity type overlying the first region. The semiconductor device structure further comprises a second region having the first conductivity type overlying the buried region, the second region abutting the buried region to form an electrical contact with the buried region, and a first resistance configured electrically in series with the second region and the buried region. The combined series resistance of the first resistance and the second region is greater than a resistance of the buried region.

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Tempe, AZ, United States of America

Weixiao Huang