Yibu Semiconductor Co., Ltd.

Lear Corporation

Weiping Li

XiaoZhong Wu

Yue Zuo

Cheng Zhan

Yaoju Song

Chaoyan Zhan

A semiconductor packaging method, a semiconductor assembly and an electronic device are disclosed herein. The semiconductor packaging method comprises forming a first-level assembly, including: align and fix at least one first-level device to a target position on a carrier plate by utilizing the self-alignment capability of first-level alignment solder joints; encapsulating the at least one first-level device to form a molded package body; and exposing the first-level interconnect terminals from the molded package body. The packaging method further comprises align and fix a second-level device to a target position on the first-level assembly by utilizing the self-alignment capability of second-stage alignment solder joints between the first-level assembly and the second-level device. The packaging method improves the operation speed and accuracy of the picking and placing of the first-level device and the second-level device, resulting in improved process efficiency and reduced process cost.

Semiconductor packaging method, semiconductor assembly and electronic device comprising semiconductor assembly

A method of forming a package comprises assembling at least one chip layer over a carrier substrate, the at least one chip layer including chip couplers and chips, each of the chips having a front side facing the carrier substrate and chip contacts formed on the front side, the couplers including first chip couplers, each of the first chip couplers having an upper side facing away from the carrier substrate and first bumps formed on the upper side. The method further comprises encapsulating the at least one chip layer to form a molded package structure, thinning the molded package structure to expose the first bumps, forming a metal layer on a side of the molded package structure where the first bumps are exposed, removing the carrier to expose another side of the molded package structure, and forming a redistribution layer and second bumps on the molded package structure.

Chip package and method of forming chip packages

A method of forming a package comprises forming a stack of chip layers on a carrier. The stack of chip layers including at least a first chip layer over the carrier and a second chip layer over the first chip layer. The first chip layer includes a plurality of first chips facing the carrier and a plurality of chip couplers. The second chip layer includes a plurality of second chips facing the first chip layer. The method further comprises encapsulating the stack of chip layers in a molding compound, removing the carrier to expose the front side of the first chip layer, forming a redistribution layer on the front side of the first chip layer and bumps on the redistribution layer, and dividing the stack of chips and the redistribution layer to form a plurality of the packages. A chip package thus formed include a stack of chips and one or more chip connectors on a singulated redistribution layer.

The present disclosure provides a method for forming a semiconductor package and a semiconductor package. The method comprises providing a semiconductor wafer with at least one semiconductor device formed thereon, the at least one semiconductor device comprising a plurality of metal bond pads formed on the semiconductor wafer. The method further comprises forming a first photoresist layer having a first opening directly above at least a portion of a first metal bond pad; forming a first metal feature of a first height in the first opening; removing the first photoresist layer; forming a second photoresist layer having a second opening directly above at least a portion of the second metal bond pad; forming a second metal feature of a second height in the second opening; and removing the second photoresist layer. Using the method, metal bumps having different heights and different sizes can be formed in a controlled manner.

Method for forming semiconductor package and semiconductor package

A method of forming a package is provided. The method comprises assembling on a carrier a stack of chip layers including a plurality of first chip layers and a second chip layer; encapsulating the stack of chip layers in a molding compound; removing the carrier to form a package main body; forming a redistribution layer on an exposed side of a first chip layer; and dividing the package main body to form a plurality of packages. Each first chip layer includes first chips and chip couplers. A chip package includes at least one chip stack and at least one chip coupler stack on a singulated redistribution layer. Each chip stack includes at least one chip from each chip layer, and each chip coupler stack includes at least one chip coupler and/or at least one chip coupler segment from each of the first chip layers.

Method of forming packages of stacked chips

The present application provides a method for forming chip packages and a chip package. The method comprises arranging a plurality of interconnect devices at intervals on a surface of a carrier and assembling a plurality of chipsets over the interconnect devices. Each chipset comprises at least two chips electrically connected through an interconnect device. A front surface of each chip facing the carrier is provided with a plurality of first bumps. The method further comprises forming a molded package layer whereby the plurality of chipsets and the plurality of interconnect devices are embedded in the molded package layer; removing the carrier and thinning the molded package layer to expose the first bumps; forming second bumps on the surface on one side of the molded package layer where the first bumps are exposed; and dicing the molded package layer to obtain a plurality of package units. Thus, a flexible and low-cost packaging scheme is provided for multi-chip interconnection.

Method for forming chip packages and a chip package

The present disclosure provides a chip interconnecting method, an interconnect device and a method for forming a chip interconnection package. The method comprises arranging at least one chipset on a carrier, each chipset including at least a first chip and a second chip. A contact surface (or diameter) of each of the first bumps is smaller than that of any of the second bumps. The method further comprises attaching an interconnect device to the first chip and the second chip, the interconnect device including first pads for bonding to corresponding bumps on the first chip and second pads for bonding to corresponding bumps on the second chip. Attaching the interconnect device includes aligning the plurality of first pads with the corresponding bumps on the first chip whereby the plurality of second pads are self-aligned for bonding to the plurality of second bumps.

Chip interconnecting method, interconnect device and method for forming chip packages

A semiconductor packaging method, a semiconductor assembly and an electronic device are disclosed herein. The semiconductor packaging method comprises providing at least one semiconductor device and a first carrier board. The at least one semiconductor device has a passive surface with first alignment solder parts formed thereon, and the first carrier board has a plurality of corresponding second alignment solder parts formed thereon. The method further comprises forming alignment solder joints by aligning and soldering the first alignment solder parts to respective ones of the second alignment solder parts; removing the first carrier board after attaching a second carrier board to the active surface of the at least one semiconductor device; forming a molded package body on one side of the second carrier board to encapsulate the at least one semiconductor device; and removing the second carrier board to expose the connecting terminals.

A semiconductor packaging method, a semiconductor assembly and an electronic device are disclosed herein. The semiconductor packaging method comprises providing at least one semiconductor device, a carrier board, and a clamping board. The at least one semiconductor device has a passive surface with first alignment solder parts formed thereon, and the carrier board has a plurality of corresponding second alignment solder parts formed thereon. The method further comprises forming alignment solder joints by aligning and soldering the first alignment solder parts to respective ones of the second alignment solder parts; and injecting a molding compound through one or more openings in one or both of the carrier board and the clamping board to form a molded package body encapsulating the at least one semiconductor device between the carrier board and the clamping board attached to the active surface of the at least one semiconductor device.

A semiconductor packaging method, a semiconductor assembly and an electronic device are disclosed herein. The semiconductor packaging method comprises forming a first-stage assembly, including: align and fix at least one first-stage device to a target position on a carrier plate by utilizing the self-alignment capability of first-stage alignment solder joints; and while using a clamping board to support an exposed side of the at least one first-stage device, performing injection molding through an opening in the carrier board or the clamping board. The packaging method further comprises align and fix a second-stage device to a target position on the first-stage assembly by utilizing the self-alignment capability of second-level alignment solder joints between the first-stage assembly and the second-stage device. The packaging method improves the operation speed and accuracy of the picking and placing of the first-stage device and the second-stage device, resulting in improved process efficiency and reduced process cost.

The present disclosure provides a method for forming a semiconductor package and the semiconductor package. The method comprises attaching an interconnect device to a semiconductor substrate, and flip-chip mounting at least two chips over the interconnect device and the semiconductor substrate. Each chip includes at least one first bump of a first height and at least one second bump of a second height formed on a front surface hereof, the second height being greater than the first height. The method further comprises bonding the at least one second conductive bump of each of the at least two chips to the upper surface of the semiconductor substrate and bonding the first conductive bump of each of the at least two chips to the upper surface of the interconnect device Thus, the method uses a relatively simple and low cost packaging process to achieve high-density interconnection wiring in a package.

The present application provides a method for forming a chip package and a chip package. The method comprises mounting at least one chipset including at least first and second chips on a carrier with front surface of the chips face away from the carrier; attaching an interconnection device to the front surfaces of the first and second chips to enable electrically connections between the chips; forming a molded encapsulation layer whereby the first chip, the second chip and the interconnection device are embedded or partially embedded in the molded encapsulation layer; thinning one side of the molded encapsulation layer away from the carrier to expose first bumps on the first and second chips; forming second bumps on a surface of one side of the molded encapsulation layer where the first bumps are exposed; and removing the carrier. Thus, a flexible, efficient and low-cost packaging scheme is provided for multi-chip connection.

Method for forming chip packages and a chip package having a chipset comprising a first chip and a second chip

A method of forming a package comprises forming a stack of chip layers. Each chip layer has a front side facing away from the carrier substrate. A first chip layer includes a plurality of first chips having first chip contacts on the front side of the first chip layer and chip couplers having through vias. A second chip layer includes a plurality of second chip having second chip contacts on the front side of the second chip layer and coupled to respective ones of at least a first subset of the through vias. The method further comprises forming a redistribution layer on the front side of the first chip layer and dividing the stack of chip layers and the redistribution layer to form a plurality of chip packages. A chip package thus formed include a stack of chips and one or more chip connectors on a singulated redistribution layer.

Method of forming chip package having stacked chips

A semiconductor packaging method, a semiconductor assembly and an electronic device comprising the semiconductor assembly are described herein. The semiconductor packaging method comprises providing at least one semiconductor device and a carrier board. A plurality of first alignment solder parts are formed on an active surface of each semiconductor device in addition to connection terminals. A plurality of second alignment solder parts are formed on a surface of the carrier board. The method further comprises forming a plurality of alignment solder joints by aligning and soldering the first alignment solder parts to respective ones of the second alignment solder parts whereby the semiconductor device is aligned and fixed to the carrier board; encapsulating the at least one semiconductor device to form a molded package body; sequentially forming a redistribution layer and external terminals on the molded package body so that the connection terminals are connected to the external terminal through the interconnection layer.

Growing community of inventors

Shanghai, China

Weiping Li