Applied Materials, Inc.

Weifeng Ye

Li-Qun Xia

Mei-Yee Shek

Mehul B Naik

He Ren

Yong Cao

Yana Cheng

Deenesh Padhi

Paul F Ma

David P Thompson

Xianmin Tang

Kelvin Chan

Mihaela A Balseanu

Kang Sub Yim

Kevin Vincent Moraes

Srinivas Guggilla

Xiaolan Ba

Sree Rangasai V Kesapragada

Yu Jin

Feng Quan Liu

Avgerinos V Gelatos

Alexandros T Demos

Xinyu Fu

Sang Ho Yu

Derek R Witty

Victor Nguyen

Jiang Lu

Hua Ai

Xiaojun Zhang

In some embodiments, a method of forming an interconnect structure includes selectively depositing a barrier layer atop a substrate having one or more exposed metal surfaces and one or more exposed dielectric surfaces, wherein a thickness of the barrier layer atop the one or more exposed metal surfaces is greater than the thickness of the barrier layer atop the one or more exposed dielectric surfaces. In some embodiments, a method of forming an interconnect structure includes depositing an etch stop layer comprising aluminum atop a substrate via a physical vapor deposition process; and depositing a barrier layer atop the etch stop layer via a chemical vapor deposition process, wherein the substrate is transferred from a physical vapor deposition chamber after depositing the etch stop layer to a chemical vapor deposition chamber without exposing the substrate to atmosphere.

Methods for depositing dielectric barrier layers and aluminum containing etch stop layers

The present disclosure provides an interconnect formed on a substrate and methods for forming the interconnect on the substrate. In one embodiment, the method for forming an interconnect on a substrate includes depositing a barrier layer on the substrate, depositing a transition layer on the barrier layer, and depositing an etch-stop layer on the transition layer, wherein the transition layer shares a common element with the barrier layer, and wherein the transition layer shares a common element with the etch-stop layer.

Method to reduce trap-induced capacitance in interconnect dielectric barrier stack

Methods for selectively depositing a cobalt layer are provided herein. In some embodiments, methods for selectively depositing a cobalt layer include: exposing a substrate to a first process gas to passivate an exposed dielectric surface, wherein the substrate comprises a dielectric layer having an exposed dielectric surface and a metal layer having an exposed metal surface; and selectively depositing a cobalt layer atop the exposed metal surface using a thermal deposition process.

Methods for thermally forming a selective cobalt layer

Embodiments of the present invention provide processes to selectively form a metal layer on a conductive surface, followed by flowing a silicon based compound over the metal layer to form a metal silicide layer. In one embodiment, a substrate having a conductive surface and a dielectric surface is provided. A metal layer is then deposited on the conductive surface. A metal silicide layer is formed as a result of flowing a silicon based compound over the metal layer. A dielectric is formed over the metal silicide layer.

Cu/barrier interface enhancement

Embodiments described herein generally relate to the formation of a UV compatible barrier stack. Methods described herein can include delivering a process gas to a substrate positioned in a process chamber. The process gas can be activated to form an activated process gas, the activated process gas forming a barrier layer on a surface of the substrate, the barrier layer comprising silicon, carbon and nitrogen. The activated process gas can then be purged from the process chamber. An activated nitrogen-containing gas can be delivered to the barrier layer, the activated nitrogen-containing gas having a N:NHratio of greater than about 1:1. The activated nitrogen-containing gas can then be purged from the process chamber. The above elements can be performed one or more times to deposit the barrier stack.

Enhancing electrical property and UV compatibility of ultrathin blok barrier film

Embodiments of the invention provide processes to selectively form a cobalt layer on a copper surface over exposed dielectric surfaces. Embodiments described herein control selectivity of deposition by preventing damage to the dielectric surface, repairing damage to the dielectric surface, such as damage which can occur during the cobalt deposition process, and controlling deposition parameters for the cobalt layer.

Cobalt selectivity improvement in selective cobalt process sequence

A method for the removal of copper oxide from a copper and dielectric containing structure of a semiconductor chip is provided. The copper and dielectric containing structure may be planarized by chemical mechanical planarization (CMP) and treated by the method to remove copper oxide and CMP residues. Annealing in a hydrogen (H) gas and ultraviolet (UV) environment removes copper oxide, and a pulsed ammonia plasma removes CMP residues.

Copper oxide removal techniques

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San Jose, CA, United States of America

Weifeng Ye