Taiwan Semiconductor Manufacturing Comp. Ltd.

Tsinghua University

National Central University

Wei-Yen Woon

Mrunal Abhijith Khaderbad

Cheng-Ming Lin

Han-Yu Lin

Szuya Liao

Szu-Hua Chen

Jhih-Rong Huang

Kuan-Kan Hu

Li-Te S Lin

Chun-Feng Nieh

Yi-Bo Liao

Ching-Yi Chen

Kenichi Sano

Hsun Chang

Chung-Ru Yang

Che Chi Shih

Pinyen Lin

Tai-Chun Huang

Ku-Feng Yang

Shuen-Shin Liang

Tzer-Min Shen

Ming-Chang Wen

Ming-Jie Huang

Ting-Gang Chen

Tze-Chung Lin

Yen-Tien Tung

Dhanyakumar Mahaveer Sathaiya

Sung-li Wang

Hsin Yang Hung

Po-Cheng Wang

Che-Chi Shih

Tsung-Kai Chiu

Kuramitsu Yasuhiro

Hsu-Sheng Tsai

Min-Chiang Chuang

Jenq-Horng Liang

A device includes a first semiconductor structure, a second semiconductor structure, and an isolation structure which is disposed between the first and second semiconductor structures, and which includes a dielectric material having a dielectric constant higher than 8 and lower than 16. A method for manufacturing the device is also disclosed.

Isolation structure for semiconductor device

A method is provided that includes depositing a catalyst layer along a surface of the opening and performing a selectivity enhancement process. The selectivity enhancement process alters a deposition rate of a metal component on at least one region of the catalyst layer. The metal component is deposited on the catalyst layer. Exemplary selectivity enhancement processes include a self-assembled monolayer (SAM), introducing an accelerator, and/or introducing a suppressor.

Metal features of a semiconductor device and methods for forming the same

An integrated circuit (IC) with a semiconductor device and an interconnect structure with carbon layers and methods of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a source/drain region on the fin structure, forming a contact structure on the S/D region, forming an oxide layer on the contact structure, forming a conductive carbon line within a first insulating carbon layer on the oxide layer, forming a second insulating carbon layer on the first insulating carbon layer, and forming a via within the second insulating carbon layer.

Interconnect structures with conductive carbon layers

A method for manufacturing a semiconductor device is provided. The method includes forming a first transistor over a substrate, wherein the first transistor comprises a first source/drain feature; depositing an interlayer dielectric layer around the first transistor; etching an opening in the interlayer dielectric layer to expose the first source/drain feature; conformably depositing a semimetal layer over the interlayer dielectric layer, wherein the semimetal layer has a first portion in the opening in the interlayer dielectric layer and a second portion over a top surface of the interlayer dielectric layer; and forming a source/drain contact in the opening in the interlayer dielectric layer.

Semiconductor device and manufacturing method thereof

A semiconductor device having a low-k isolation structure and a method for forming the same are provided. The semiconductor device includes channel structures, laterally extending on a substrate; gate structures, intersecting and covering the channel structures; and a channel isolation structure, laterally penetrating through at least one of the channel structures, and extending between separate sections of one of the gate structures along an extending direction of the one of the gate structures. A low-k dielectric material in the channel isolation structure comprises boron nitride.

Semiconductor device having isolation structure formed of low-k dielectric material and method for forming the same

The present disclosure describes a semiconductor device and a method for forming the semiconductor device. The method includes forming a fin structure on a substrate, forming a gate structure on the fin structure, and forming a source/drain (S/D) region on the fin structure not covered by the gate structure. The method further includes forming a contact structure on the S/D region. Forming the contact structure includes forming a transition metal chalcogenide (TMC) layer on the S/D region, and forming a contact plug on the TMC layer.

Contact structures in semiconductor devices

The present disclosure provides source/drain epitaxial structures and source/drain contacts wrapped with graphene layers in fin structures of field effect transistors, and fabricating methods thereof. In some embodiments, a disclosed semiconductor device includes a fin structure on a substrate. The fin structure includes an epitaxial region. The semiconductor device further includes a metal contact above the epitaxial region, and a graphene film covering a top surface and sidewalls of the epitaxial region and covering a bottom surface and sidewalls of the metal contact.

Graphene wrap-around contact

The present disclosure provides a method that includes providing a semiconductor structure having a bottom channel region and a top channel region over the bottom channel region; forming a gate dielectric layer over and wrapping around top channels in the top channel region; performing a radical treatment on the dielectric layer in a supercritical fluid; and forming a metal gate electrode on the dielectric layer.

Radical treatment in supercritical fluid for gate dielectric quality improvement to CFET structure

The present disclosure describes a 2D channel FET with low contact resistance and a method for forming such a structure. The method includes depositing a dielectric layer on a semiconductor substrate, depositing a metal layer on the dielectric layer, and depositing a hard mask layer on the metal layer. The method further includes forming a gate opening by removing a portion of the hard mask layer and a portion of the metal layer. The method further includes depositing a spacer material layer on sidewalls of the gate opening and forming a channel, the channel including a TMC layer, at a bottom of the gate opening. The method further includes forming a gate structure on the channel and in the gate opening and removing the hard mask layer.

2D channel transistors with low contact resistance

A semiconductor structure includes a semiconductor substrate, a first source/drain portion, a second source/drain portion, a first metal contact, a second metal contact and a first conductive carbon layer. The first and second source/drain portions are formed over the semiconductor substrate, and are spaced apart from each other. The first source/drain portion has a conductivity type different from that of the second source/drain portion. The first and second metal contacts are respectively formed on the first and second source/drain portions. The first conductive carbon layer is formed between the first source/drain portion and the first metal contact.

Semiconductor structure with conductive carbon layer and method for manufacturing the same

The present disclosure provides low resistance contacts and damascene interconnects with one or more graphene layers in fin structures of FETs. An example semiconductor device can include a substrate with a fin structure that includes an epitaxial region. The semiconductor device can also include an etch stop layer on the epitaxial region, and an interlayer dielectric layer on the etch stop layer. The semiconductor device can further include a metal contact, above the epitaxial region, formed through the etch stop layer and the interlayer dielectric layer, and a graphene film at interfaces between the metal contact and each of the epitaxial region, the etch stop layer, and the interlayer dielectric layer.

Graphene layer for low resistance contacts and damascene interconnects

A semiconductor device includes a semiconductor feature, a low-k dielectric feature that is formed on the semiconductor feature, and a Si-containing layer that contains elements of silicon and that covers over the low-k dielectric feature. The Si-containing layer can prevent the low-k dielectric feature from being damaged in etch and/or annealing processes for manufacturing the semiconductor device.

Semiconductor device, and method for protecting low-k dielectric feature of semiconductor device

A method includes forming Complementary Field-Effect Transistors including a lower transistor comprising a lower source/drain region, and an upper transistor including an upper source/drain region. An upper dielectric layer over the upper source/drain region and a lower dielectric layer under the upper source/drain region are etched to form an opening. A sidewall of the upper source/drain region and a top surface of the lower source/drain region are exposed to the opening. An epitaxy process is performed to form a first semiconductor layer on the sidewall of the upper source/drain region, and a second semiconductor layer on the top surface of the lower source/drain region. The first semiconductor layer is then removed. A contact plug is formed in the opening to electrically connects the upper source/drain region to the second semiconductor layer and the lower source/drain region.

Selective epitaxy process for the formation of CFET local interconnection

The present disclosure describes a semiconductor device with a rare earth metal oxide layer and a method for forming the same. The method includes forming fin structures on a substrate and forming superlattice structures on the fin structures, where each of the superlattice structures includes a first-type nanostructured layer and a second-type nanostructured layer. The method further includes forming an isolation layer between the superlattice structures, implanting a rare earth metal into a top portion of the isolation layer to form a rare earth metal oxide layer, and forming a polysilicon structure over the superlattice structures. The method further includes etching portions of the superlattice structures adjacent to the polysilicon structure to form a source/drain (S/D) opening and forming an S/D region in the S/D opening.

Semiconductor devices with a rare earth metal oxide layer

The present invention relates to an ion generation composite target for an ion irradiation technology including: a substrate having a through hole formed thereon; and a graphene thin film configured on the substrate, across the through hole, having a thickness in a range between 1 nm to 3 nm, and ionized to release a proton or a carbon ion.

Growing community of inventors

Taoyuan, Taiwan

Wei-Yen Woon