Taiwan Semiconductor Manufacturing Comp. Ltd.

National Taiwan University

Taiwan Semincodcutor Manufacturing Company, Ltd.

Wei-Yang Lee

Feng-Cheng Yang

Yen-Ming Chen

Chia-Pin Lin

Feng-Ching Chu

Yen-Ting Chen

Ting-Yeh Chen

Yuan-Ching Peng

Kuang-Yuan Hsu

I-Hsieh Wong

Tzu-Hsiang Hsu

Bo-Yu Lai

Tzu-Hua Chiu

Wei-Han Fan

Chun Hsiung Tsai

Da-Yuan Lee

Chen-Ming Lee

Kai-Hsuan Lee

Xiong-Fei Yu

Chien-Tai Chan

Po-Yu Lin

Chih-Shan Chen

Che-Lun Chang

Kuan-Hao Cheng

Fu-Kai Yang

Da-Wen Lin

Wei-Yuan Lu

Cheng-Yu Yang

Kuan-Lun Cheng

Jian-Hao Chen

Chia-Ling Chan

LI-Li Su

Yee-Chia Yeo

Chung-Te Lin

Chien-Wei Lee

Wei Hao Lu

Shih-Chiang Chen

Chia-Chun Lan

Chih-Hao Wang

Sai-Hooi Yeong

Shahaji B More

Chii-Horng Li

Tsung-Lin Lee

Cheng-Yi Peng

Kuo-Feng Yu

Wen-Hsing Hsieh

Chien-I Kuo

Ming-Chang Wen

Cheng-Hao Hou

Chien Ning Yao

Ya-Yun Cheng

Yi-Hsiu Liu

Kai-Di Tzeng

Po-Shao Lin

Jo-Tzu Hung

Ruei-Ping Lin

Mei-Yun Wang

Hun-Jan Tao

Hsueh-Chang Sung

Kun-Mu Li

De-Fang Chen

Chun-Hsiung Tsai

Jiun-Ming Kuo

Chih-Hao Yu

Jean-Fu Kiang

Wei-Min Liu

Wen-Chu Hsiao

Chih-Ching Wang

Yen-Po Lin

Jin-Mu Yin

Te-En Cheng

Jyun-Chih Lin

Wei-Hao Lu

Meng-Hsuan Chan

Chun Po Chang

Chi On Chui

Chih-Chiang Chang

Yung-Cheng Lu

Dian-Hau Chen

Kuan-Ting Pan

Kuo-Yi Chao

Li-Li Su

Kuan-lun Cheng

Wei-Ken Lin

Wen-Kai Lin

Ming-Lung Cheng

Matt Yeh

Han-Wei Wu

Wei-Jen Lai

Shu-Wen Shen

Szu-Wei Tseng

Chih-Hung Nien

Wei-Yeh Tang

Tzu-Wei Kao

Chih-Hsin Yang

Chung-Chi Wen

Po-Cheng Wang

Bang-Ting Yan

Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method of manufacture comprises receiving a substrate including a semiconductor material stack formed thereon, wherein the semiconductor material stack includes a first semiconductor layer of a first semiconductor material and second semiconductor layer of a second semiconductor material that is different than the first semiconductor material. Patterning the semiconductor material stack to form a trench. The patterning includes performing a first etch process with a first etchant for a first duration and then performing a second etch process with a second etchant for a second duration, where the second etchant is different from the first etchant and the second duration is greater than the first duration. The first etch process and the second etch process are repeated a number of times. Then epitaxially growing a third semiconductor layer of the first semiconductor material on a sidewall of the trench.

Semiconductor device active region profile and method of forming the same

Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises semiconductor layers over a substrate, wherein the semiconductor layers are stacked up and separated from each other, each semiconductor layer includes a first portion in a first channel region of the substrate and a second portion in a second channel region of the substrate, epitaxial layers formed in a source/drain region between the first channel region and the second channel region, wherein the epitaxial layers are separated from each other and each epitaxial layer is formed between the first portion and the second portion of each semiconductor layer, and a conductive feature wrapping each of the epitaxial layers.

Semiconductor device with epitaxial bridge feature and methods of forming the same

Multi-gate devices and methods for fabricating such are disclosed herein. An exemplary method includes forming a semiconductor stack on a substrate, wherein the semiconductor stack includes a first semiconductor layers and a second semiconductor layers alternatively disposed, the first semiconductor layers and the second semiconductor layers being different in composition; patterning the semiconductor stack to form a semiconductor fin; forming a dielectric fin next to the semiconductor fin; forming a first gate stack on the semiconductor fin and the dielectric fin; etching to a portion of the semiconductor fin within a source/drain region, resulting in a source/drain recess; and epitaxially growing a source/drain feature in the source/drain recess, defining an airgap spanning between a sidewall of the source/drain feature and a sidewall of the dielectric fin.

Source and drain engineering process for multigate devices

In a method of manufacturing a semiconductor device, a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked is formed over a substrate, a sacrificial gate structure is formed over the fin structure, a source/drain region of the fin structure is etched thereby forming a source/drain space, ends of the first semiconductor layers is laterally etched, an insulating layer is formed on a sidewall of the source/drain space, the insulating layer is partially etched, thereby forming one or more inner spacers on an etched end face of each of one or more first semiconductor layers and leaving a part of the insulating layer as a remaining insulating layer, and a source/drain epitaxial layer is formed in the source/drain space. After the source/drain epitaxial layer is formed, an end face of at least one of the second semiconductor layers is covered by the remaining insulating layer.

Methods of manufacturing semiconductor devices and semiconductor devices

A semiconductor device includes a substrate; two source/drain (S/D) regions over the substrate; a gate stack over the substrate and between the two S/D regions; a spacer layer covering sidewalls of the gate stack; an S/D contact metal over one of the two S/D regions; a first dielectric layer covering sidewalls of the S/D contact metal; and an inter-layer dielectric (ILD) layer covering the first dielectric layer, the spacer layer, and the gate stack, thereby defining a gap. A material of a first sidewall of the gap is different from materials of a top surface and a bottom surface of the gap, and a material of a second sidewall of the gap is different from the materials of the top surface and the bottom surface of the gap.

Semiconductor device with air-spacer

A method for manufacturing an integrated circuit (IC) structure is provided. The method includes: etching a first recess and a second recess in a substrate; forming a sacrificial epitaxial plug in the first recess in the substrate; forming a first epitaxial feature and a second epitaxial feature respectively in the first recess and the second recess, wherein the first epitaxial feature is over the sacrificial epitaxial plug; forming a first source/drain epitaxial structure and a second source/drain epitaxial structure over the first epitaxial feature and the second epitaxial feature respectively; forming a gate structure laterally between the first source/drain epitaxial structure and the second source/drain epitaxial structure; removing the sacrificial epitaxial plug and the first epitaxial feature to form a backside via opening exposing a backside of the first source/drain epitaxial structure; and forming a backside via in the backside via opening.

Integrated circuit structure

A semiconductor structure includes an isolation structure; first and second source/drain (S/D) features over the isolation structure, defining a first direction from the first S/D feature to the second S/D feature from a top view; one or more channel layers connecting the first and the second S/D features; a gate structure between the first and the second S/D features and engaging each of the one or more channel layers; and a via structure under the first S/D feature and electrically connecting to the first S/D feature. In a cross-sectional view perpendicular to the first direction, the via structure has a profile that widens and then narrows along a bottom-up direction.

Epitaxial source/drain feature with enlarged lower section interfacing with backside via

Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a semiconductor fin formed on a substrate; and a gate structure disposed over a channel region of the semiconductor fin, the gate structure including a gate dielectric layer and a gate electrode, wherein the gate dielectric layer includes a bottom portion and a side portion, and the gate electrode is separated from the side portion of the gate dielectric layer by a first air gap.

FinFET structure with airgap and method of forming the same

A device a includes a substrate, two source/drain (S/D) features over the substrate, and semiconductor layers suspended over the substrate and connecting the two S/D features. The device further includes a dielectric layer disposed between two adjacent layers of the semiconductor layers and an air gap between the dielectric layer and one of the S/D features, where a ratio between a length of the air gap to a thickness of the first dielectric layer is in a range of 0.1 to 1.0.

Method and structure for air gap inner spacer in gate-all-around devices

A semiconductor device including a fin field effect transistor (FinFET) with a cut metal gate (CMG) and a method of manufacturing the semiconductor device are described herein. The method includes forming a CMG protective helmet structure at a top portion of a CMG dummy gate plug formed within a semiconductor substrate. The CMG protective helmet structure prevents consumption and damage of a dummy filler material in a CMG region and prevents undesirable polymer/residue byproducts from forming on top surfaces of epitaxial regions of the FinFET during etching processes.

Semiconductor device and method

A semiconductor device structure is provided. The semiconductor device structure includes a stack of channel structures and a first epitaxial structure and a second epitaxial structure adjacent to opposite sides of the channel structures. The semiconductor device structure also includes a gate stack wrapped around the channel structures and a backside conductive contact connected to the second epitaxial structure. The second epitaxial structure is between a top of the backside conductive contact and a top of the gate stack. The semiconductor device structure further includes an etch stop layer extending along a sidewall of the backside conductive contact and a bottom of the gate stack.

Semiconductor device structure with backside contact

A method includes forming a semiconductor fin protruding from a substrate, forming a dummy gate structure across the semiconductor fin, recessing a portion of the semiconductor fin in a region adjacent the dummy gate structure to form a recess, growing a semiconductor layer in the recess, and forming a first dielectric layer interposing the semiconductor layer and the dummy gate structure. The semiconductor layer covers at least a portion of the first dielectric layer. The method also includes modifying a shape of the semiconductor layer to expose the portion of the first dielectric layer, depositing a second dielectric layer covering the semiconductor layer and the portion of the first dielectric layer, and replacing the dummy gate structure with a metal gate structure.

Epitaxial features in semiconductor devices and manufacturing method of the same

A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base and a fin over the base. The semiconductor device structure includes a gate stack over a top portion of the fin. The semiconductor device structure includes a first nanostructure over the fin and passing through the gate stack. The semiconductor device structure includes a second nanostructure over the first nanostructure and passing through the gate stack. The first nanostructure is thicker than the second nanostructure. The semiconductor device structure includes a stressor structure over the fin and connected to the first nanostructure and the second nanostructure.

Semiconductor device structure and method for forming the same

A method includes providing a structure having a substrate, fins and an isolation structure over the substrate, wherein each fin includes first and second semiconductor layers alternatingly stacked. The method further includes depositing a first dielectric layer over top and sidewalls of the fins and over a top surface of the isolation structure; depositing a second dielectric layer over the first dielectric layer; and etching back the first and the second dielectric layers such that they remain on the top surface of the isolation structure and are removed from the top and sidewalls of the fins. The method further includes forming dummy gate stacks, gate spacers, source and drain trenches, and inner spacers, wherein the first and the second dielectric layers remain on the top surface of the isolation structure.

Isolation structures in multi-gate field-effect transistors

A method includes forming a structure having a dummy gate stack over a fin protruding from a substrate. The fin includes an ML of alternating semiconductor layers and sacrificial layers. The method further includes forming a recess in an S/D region of the ML, forming a recess of the ML, and forming inner spacers on sidewalls of the sacrificial layers. Each inner spacer includes a first layer embedded in the sacrificial layer and a second layer over the first layer. The method further includes forming an S/D feature in the recess, such that the second layer of the inner spacers is embedded in the S/D feature. The method further includes removing the dummy gate stack to form a gate trench, removing the sacrificial layers from the ML, thereby forming openings interleaved between the semiconductor layers, and subsequently forming a high-k metal gate stack in the gate trench and the openings.

Dielectric inner spacers in multi-gate field-effect transistors

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Taipei, Taiwan

Wei-Yang Lee