Taiwan Semiconductor Manufacturing Comp. Ltd.

National Taiwan University

Taiwan Semincodcutor Manufacturing Company, Ltd.

Wei-Yang Lee

Feng-Cheng Yang

Yen-Ming Chen

Chia-Pin Lin

Feng-Ching Chu

Yen-Ting Chen

Ting-Yeh Chen

Yuan-Ching Peng

Kuang-Yuan Hsu

I-Hsieh Wong

Tzu-Hsiang Hsu

Tzu-Hua Chiu

Bo-Yu Lai

Wei-Han Fan

Chun Hsiung Tsai

Da-Yuan Lee

Chen-Ming Lee

Kai-Hsuan Lee

Kuan-Hao Cheng

Xiong-Fei Yu

Chien-Tai Chan

Po-Yu Lin

Chih-Shan Chen

Che-Lun Chang

Fu-Kai Yang

Da-Wen Lin

Wei-Yuan Lu

Cheng-Yu Yang

Kuan-Lun Cheng

Jian-Hao Chen

Chia-Ling Chan

LI-Li Su

Yee-Chia Yeo

Chung-Te Lin

Tsung-Lin Lee

De-Fang Chen

Chien-Wei Lee

Wei Hao Lu

Shih-Chiang Chen

Chia-Chun Lan

Chih-Hao Wang

Sai-Hooi Yeong

Shahaji B More

Chii-Horng Li

Cheng-Yi Peng

Kuo-Feng Yu

Wen-Hsing Hsieh

Chien-I Kuo

Ming-Chang Wen

Cheng-Hao Hou

Chien Ning Yao

Ya-Yun Cheng

Yi-Hsiu Liu

Kai-Di Tzeng

Po-Shao Lin

Jo-Tzu Hung

Ruei-Ping Lin

Mei-Yun Wang

Hun-Jan Tao

Dian-Hau Chen

Hsueh-Chang Sung

Kun-Mu Li

Chun-Hsiung Tsai

Jiun-Ming Kuo

Chih-Hao Yu

Jean-Fu Kiang

Wei-Jen Lai

Wei-Min Liu

Wen-Chu Hsiao

Chih-Ching Wang

Yen-Po Lin

Te-En Cheng

Jin-Mu Yin

Jyun-Chih Lin

Wei-Hao Lu

Chih-Hsin Yang

Meng-Hsuan Chan

Po-Cheng Wang

Chi On Chui

Chao-Cheng Chen

Chih-Chiang Chang

Yung-Cheng Lu

Kuan-Ting Pan

Kuo-Yi Chao

Li-Li Su

Kuan-lun Cheng

Wei-Ken Lin

Wen-Kai Lin

Ming-Shuan Li

Ming-Lung Cheng

Matt Yeh

Han-Wei Wu

Shu-Wen Shen

Szu-Wei Tseng

Chih-Hung Nien

Wei-Yeh Tang

Tzu-Wei Kao

Chung-Chi Wen

A method includes forming a stack of channel layers and sacrificial layers over a substrate, patterning the stack to form a fin-shape structure, and recessing a portion of the fin-shape structure to form a recess. A top surface of the substrate under the recess is covered at least by a bottommost sacrificial layer of the stack. The method also includes forming inner spacers on terminal ends of the sacrificial layers that are above the bottommost sacrificial layer, depositing an undoped layer in the recess, and forming a doped epitaxial feature over the undoped layer. The undoped layer covers terminal ends of a bottommost channel layer of the stack. The doped epitaxial feature covers terminal ends of the channel layers that are above the bottommost channel layer.

Epitaxial features in semiconductor devices and method of manufacturing

A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary semiconductor method includes forming a fin-shaped structure extending from a substrate, the fin-shaped structure includes a number of channel layers interleaved by a number of sacrificial layers, recessing a source/drain region to form a source/drain opening, performing a PAI process to amorphize a portion of the substrate exposed by the source/drain opening, forming a tensile stress film over the substrate, performing an annealing process to recrystallize the portion of the substrate, the recrystallized portion of the substrate includes dislocations, forming an epitaxial source/drain feature over the source/drain opening, and forming a gate structure wrapping around each of the plurality of channel layers. By performing the above operations, dislocations are controllably and intentionally formed and carrier mobility in the number of channel layers may be advantageously enhanced, leading to improved device performance.

Semiconductor devices with enhanced carrier mobility

A method of fabricating a device includes providing a fin having a stack of epitaxial layers including a plurality of semiconductor channel layers interposed by a plurality of dummy layers. A source/drain etch process is performed to remove portions of the stack of epitaxial layers in source/drain regions to form trenches that expose lateral surfaces of the stack of epitaxial layers. A dummy layer recess process is performed to laterally etch the plurality of dummy layers to form recesses along sidewalls of the trenches. An inner spacer material is deposited along sidewalls of the trenches and within the recesses. An inner spacer etch-back process is performed to remove the inner spacer material from the sidewalls of the trenches and to remove a portion of the inner spacer material from within the recesses to form inner spacers having a dish-like region along lateral surfaces of the inner spacers.

Inner spacer for a multi-gate device and related methods

A semiconductor device includes a substrate. A gate structure is disposed over the substrate in a vertical direction. The gate structure extends in a first horizontal direction. An air spacer is disposed adjacent to a first portion of the gate structure in a second horizontal direction that is different from the first horizontal direction. The air spacer has a vertical boundary in a cross-sectional side view defined by the vertical direction and the first horizontal direction.

Selective gate air spacer formation

A semiconductor structure includes semiconductor layers vertically stacked above a substrate, a gate structure wrapping around each of the semiconductor layers, a gate spacer disposed on sidewalls of the gate structure, a source/drain (S/D) feature abutting the semiconductor layers, and an S/D contact landing on a top surface of the S/D feature. In a cross-sectional view along a lengthwise direction of the semiconductor layers, a topmost point of the top surface of the S/D feature is above a top surface of a topmost one of the semiconductor layers, and a bottommost point of the top surface of the S/D feature is below the top surface of the topmost one of the semiconductor layers.

Semiconductor devices with modified source/drain feature and methods thereof

A method includes forming a fin in a substrate. The fin is etched to create a source/drain recess. A source/drain feature is formed in the source/drain recess, in which a lattice constant of the source/drain feature is greater than a lattice constant of the fin. An epitaxy coat is grown over the source/drain feature, in which a lattice constant of the epitaxy coat is smaller than a lattice constant of the fin.

Semiconductor device

A semiconductor device according to the present disclosure includes a gate-all-around (GAA) transistor in a first device area and a fin-type field effect transistor (FinFET) in a second device area. The GAA transistor includes a plurality of vertically stacked channel members and a first gate structure over and around the plurality of vertically stacked channel members. The FinFET includes a fin-shaped channel member and a second gate structure over the fin-shaped channel member. The fin-shaped channel member includes semiconductor layers interleaved by sacrificial layers.

Method for forming different types of devices

Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method of manufacture comprises receiving a substrate including a semiconductor material stack formed thereon, wherein the semiconductor material stack includes a first semiconductor layer of a first semiconductor material and second semiconductor layer of a second semiconductor material that is different than the first semiconductor material. Patterning the semiconductor material stack to form a trench. The patterning includes performing a first etch process with a first etchant for a first duration and then performing a second etch process with a second etchant for a second duration, where the second etchant is different from the first etchant and the second duration is greater than the first duration. The first etch process and the second etch process are repeated a number of times. Then epitaxially growing a third semiconductor layer of the first semiconductor material on a sidewall of the trench.

Semiconductor device active region profile and method of forming the same

Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises semiconductor layers over a substrate, wherein the semiconductor layers are stacked up and separated from each other, each semiconductor layer includes a first portion in a first channel region of the substrate and a second portion in a second channel region of the substrate, epitaxial layers formed in a source/drain region between the first channel region and the second channel region, wherein the epitaxial layers are separated from each other and each epitaxial layer is formed between the first portion and the second portion of each semiconductor layer, and a conductive feature wrapping each of the epitaxial layers.

Semiconductor device with epitaxial bridge feature and methods of forming the same

Multi-gate devices and methods for fabricating such are disclosed herein. An exemplary method includes forming a semiconductor stack on a substrate, wherein the semiconductor stack includes a first semiconductor layers and a second semiconductor layers alternatively disposed, the first semiconductor layers and the second semiconductor layers being different in composition; patterning the semiconductor stack to form a semiconductor fin; forming a dielectric fin next to the semiconductor fin; forming a first gate stack on the semiconductor fin and the dielectric fin; etching to a portion of the semiconductor fin within a source/drain region, resulting in a source/drain recess; and epitaxially growing a source/drain feature in the source/drain recess, defining an airgap spanning between a sidewall of the source/drain feature and a sidewall of the dielectric fin.

Source and drain engineering process for multigate devices

In a method of manufacturing a semiconductor device, a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked is formed over a substrate, a sacrificial gate structure is formed over the fin structure, a source/drain region of the fin structure is etched thereby forming a source/drain space, ends of the first semiconductor layers is laterally etched, an insulating layer is formed on a sidewall of the source/drain space, the insulating layer is partially etched, thereby forming one or more inner spacers on an etched end face of each of one or more first semiconductor layers and leaving a part of the insulating layer as a remaining insulating layer, and a source/drain epitaxial layer is formed in the source/drain space. After the source/drain epitaxial layer is formed, an end face of at least one of the second semiconductor layers is covered by the remaining insulating layer.

Methods of manufacturing semiconductor devices and semiconductor devices

A semiconductor device includes a substrate; two source/drain (S/D) regions over the substrate; a gate stack over the substrate and between the two S/D regions; a spacer layer covering sidewalls of the gate stack; an S/D contact metal over one of the two S/D regions; a first dielectric layer covering sidewalls of the S/D contact metal; and an inter-layer dielectric (ILD) layer covering the first dielectric layer, the spacer layer, and the gate stack, thereby defining a gap. A material of a first sidewall of the gap is different from materials of a top surface and a bottom surface of the gap, and a material of a second sidewall of the gap is different from the materials of the top surface and the bottom surface of the gap.

Semiconductor device with air-spacer

A method for manufacturing an integrated circuit (IC) structure is provided. The method includes: etching a first recess and a second recess in a substrate; forming a sacrificial epitaxial plug in the first recess in the substrate; forming a first epitaxial feature and a second epitaxial feature respectively in the first recess and the second recess, wherein the first epitaxial feature is over the sacrificial epitaxial plug; forming a first source/drain epitaxial structure and a second source/drain epitaxial structure over the first epitaxial feature and the second epitaxial feature respectively; forming a gate structure laterally between the first source/drain epitaxial structure and the second source/drain epitaxial structure; removing the sacrificial epitaxial plug and the first epitaxial feature to form a backside via opening exposing a backside of the first source/drain epitaxial structure; and forming a backside via in the backside via opening.

Integrated circuit structure

A semiconductor structure includes an isolation structure; first and second source/drain (S/D) features over the isolation structure, defining a first direction from the first S/D feature to the second S/D feature from a top view; one or more channel layers connecting the first and the second S/D features; a gate structure between the first and the second S/D features and engaging each of the one or more channel layers; and a via structure under the first S/D feature and electrically connecting to the first S/D feature. In a cross-sectional view perpendicular to the first direction, the via structure has a profile that widens and then narrows along a bottom-up direction.

Epitaxial source/drain feature with enlarged lower section interfacing with backside via

Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a semiconductor fin formed on a substrate; and a gate structure disposed over a channel region of the semiconductor fin, the gate structure including a gate dielectric layer and a gate electrode, wherein the gate dielectric layer includes a bottom portion and a side portion, and the gate electrode is separated from the side portion of the gate dielectric layer by a first air gap.

FinFET structure with airgap and method of forming the same

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Taipei, Taiwan

Wei-Yang Lee