Texas Instruments Corporation

Wei William Lee

Maureen A Hanratty

Amitava Chatterjee

Iqbal Ali

Greg A Hames

Qizhi He

Cetin Kaya

Changming Jin

Kemal Tamer San

Jing S Shu

Quzhi He

Gilbert L Varnell

Jiong-Ping Lu

William R McKee

Kelly Jay Taylor

Hong Yang

Joseph D Luttmer

Dirk N Anderson

Richard Scott List

Ming-Jang Hwang

Richard B Timmons

John L Bartelt

Daty Michael Rogers

Larry G Venable

Steven W Russell

Albert H-b Cheng

Licheng Marshal Han

Johnny B Covington

The present invention provides integrated circuit fabrication with a silicon oxynitride antireflective layer for gate location plus patterned photoresist linewidth reduction for gate length definition followed by interconnect definition without patterned photoresist linewidth reduction. This has the advantages of an antireflective layer compatible with linewidth reduction and polysilicon etching.

Antireflective structure and method

A surface treatment for porous silica to enhance adhesion of overlying layers. Treatments include surface group substitution, pore collapse, and gap filling layer ( ) which invades open surface pores ( ) of xerogel ( ).

Porous integrated circuit dielectric with decreased surface porosity

An integrated circuit structure ( ) includes a plurality of solid state electronic devices and a plurality of conductive elements ( ) that electrically couple the electronic devices. The integrated circuit structure ( ) also includes a dielectric layer ( ) positioned between two or more of the conductive elements ( ). A liner ( ) is positioned between at least a portion of the dielectric layer ( ) and a conductive element ( ). The liner ( ) is formed from a compound that includes silicon and either carbon and nitrogen.

Dielectric layer liner for an integrated circuit structure

A gate structure which includes a semiconductor substrate having a channel region, a gate insulator adjacent the channel region of the semiconductor substrate and a conductible gate adjacent the gate insulator. A primary insulation layer is adjacent the semiconductor substrate, the primary insulation layer having an opening where the gate insulator contacts the semiconductor substrate and an isolation dielectric layer adjacent the primary insulation layer, the isolation dielectric layer having an opening where the conductible gate is located and the isolation dielectric layer having a silicon oxynitride material.

Transistor having improved gate structure

A method of reducing perfluorocarbon emissions wherein a plasma reactor or thermal chamber is provided and a gaseous single halogen-containing perfluorocarbon is entered into the reactor or thermal chamber. The perfluorocarbon is altered in the plasma reactor or thermal chamber to one of a bromine-containing and/or iodine-containing carbon species and expelled from the reactor or thermal chamber. The alteration includes entering into the plasma reactor or thermal chamber a species taken from the class consisting of iodine, bromine, hydrogen iodide, hydrogen bromide, bromocarbon compound and iodocarbon compounds. When the reactor is a thermal chamber, the temperature in the thermal chamber is at least 800&deg; C. and the single halogen-containing species is located in the chamber for from about 1 minute to about 3 minutes. When the reactor is a plasma reactor, a plasma is provided in the plasma reactor to dissociate all of the halogen-containing species in the reactor with the dissociated species combining to form more energetically favorable species which are more environmentally friendly.

Method for low perfluorocarbon compound emission

A conducting plug/contact structure for use with integrated circuit includes a tungsten conducting plug formed in the via with a tungsten-silicon-nitride (WSi N ) region providing the interface between the tungsten conducting plug and the substrate (silicon) layer. The interface region is formed providing a nitrided surface layer over the exposed dielectric surfaces and the exposed substrate surface (i.e., exposed by a via in the dielectric layer) prior to the formation of tungsten/tungsten nitride layer filling the via. The structure is annealed forming a tungsten conducting plug with a tungsten-silicon-nitride interface between the conducting plug and the substrate. According to another embodiment, a tungsten nitride surface layer is formed over the nitrided surface layer prior to the formation of a tungsten layer to fill the via. According to another embodiment, a silicon surface layer is applied to the exposed surface of the dielectric layer and to the exposed surface of the substrate prior to formation of the nitrided surface layer. A layer of tungsten, tungsten/tungsten nitride, or tungsten nitride is formed to fill the via. After annealing, a tungsten conducting plug is formed with a tungsten-silicon-nitride interface region with the substrate.

Process for high thermal stable contact formation in manufacturing sub-quarter-micron CMOS devices

A method of fabricating an improved gate structure that may be used in a transistor. A primary insulation layer ( ) may be formed adjacent a substrate ( ). A disposable gate ( ) may be formed adjacent the primary insulation layer ( ). An isolation dielectric layer ( ) may be formed adjacent the primary insulation layer ( ). The disposable gate ( ) may be removed to expose a portion of the primary insulation layer ( ). The exposed portion of the primary insulation layer ( ) may be removed to expose a portion of the substrate ( ). The primary insulation layer ( ) may be selectively removable relative to the isolation dielectric layer ( ). A gate insulator ( ) may be formed on the exposed portion of the substrate ( ). A gate ( ) may be formed adjacent the gate insulator ( ).

Transistor having an improved gate structure and method of construction

A transistor is formed on an outer surface of a substrate The transistor comprises a floating gate and a control gate An outer encapsulation layer and sidewall bodies and comprise silicon nitride that is deposited in such a manner such that the material is transmissive to ultraviolet radiation. In this manner, the sidewall bodies and and the layer can be used as an etch stop during the formation of a drain contact . These layers will also permit the transmission of ultraviolet radiation to the floating gate to enable the erasure of floating gate

Semiconductor device architectures including UV transmissive nitride layers

Integrated circuit dielectric and method

A transistor having an improved sidewall gate structure and method of construction is provided. The improved sidewall gate structure may include a semiconductor substrate (,) having a channel region (,). A gate insulation (,) may be adjacent the channel region (,) of the semiconductor substrate (,). A gate (,) may be formed adjacent the gate insulation (,). A sidewall insulation body (,) may be formed adjacent a portion of the gate (,). The sidewall insulation body (,) is comprised of a silicon oxynitride material. An epitaxial layer (,) may be formed adjacent a portion of the sidewall insulation body (,) and adjacent the semiconductor substrate (,) substantially outward of the channel region (,). A buffer layer (,) may be formed adjacent a portion of the sidewall insulation body (,) and adjacent the epitaxial layer (,).

Transistor having an improved sidewall gate structure and method of construction

A transistor,is formed on an outer surface of a substrate,. The transistor comprises a floating gate,and a control gate,. An outer encapsulation layer,and sidewall bodies,and,comprise silicon nitride that is deposited in such a manner such that the material is transmissive to ultraviolet radiation. In this manner, the sidewall bodies,and,and the layer,can be used as an etch stop during the formation of a drain contact,. These layers will also permit the transmission of ultraviolet radiation to the floating gate,to enable the erasure of floating gate

Pulsed plasma deposition of polymers as dielectrics for integrated circuit interconnects fills minimal gaps and yields a porous polymer with thermal stability by plasma off times sufficiently long to dissipate plasma on time energy input plus an anneal of the deposited polymer to drive off occluded monomers and small oligomers.

Method of forming a polymer on a surface

A transistor having an improved sidewall gate structure and method of construction is provided. The improved sidewall gate structure may include a semiconductor substrate (12) having a channel region (20). A gate insulation (36) may be adjacent the channel region (20) of the semiconductor substrate (12). A gate (38) may be formed adjacent the gate insulation (36). A sidewall insulation body (28) may be formed adjacent a portion of the gate (38). The sidewall insulation body (28) is comprised of a silicon oxynitride material. An epitaxial layer (30) may be formed adjacent a portion of the sidewall insulation body (28) and adjacent the semiconductor substrate (12) substantially outward of the channel region (20). A buffer layer (32) may be formed adjacent a portion of the sidewall insulation body (28) and adjacent the epitaxial layer (30).

Method of forming a transistor having an improved sidewall gate structure

A method of fabricating an oxidation barrier for a thin film is provided. The method may include forming a thin film (10) outwardly from a semiconductor substrate (12) and separated from the semiconductor substrate (12) by a primary insulator layer (14). A reactive layer (16) may be formed in-situ adjacent to the thin film (10). An oxidation barrier (20) may be formed by a chemical reaction between the thin film (10) and the reactive layer (16). The oxidation barrier (20) may comprise a silicide alloy that operates to reduce oxidation of the thin film (10).

Oxidation barrier composed of a silicide alloy for a thin film and

A negative resist composition including a polymeric matrix material, a polymerizable monomer, and an onium salt radiation sensitive initiator. The monomer is polymerized by irradiating the resist with an e-beam, x-ray, or ultraviolet source and heating the exposed resist. The resist is developed by a dry etchant such as plasma or a reactive ion etchant.

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Plano, TX, United States of America

Wei William Lee