United Microelectronics Corp.

United Semiconductor Corp.

Wei-Shiau Chen

Kao-Su Huang

Shu-Jen Chen

Shuenn-Jeng Chen

Ruoh-Haw Chang

Tsan-Wen Liu

A fabrication method for a multi-layered thin film protective layer, which is applicable on a substrate having a peripheral circuit area and a pixel cell area, is described. Metal layers and pixel cells are formed on the peripheral circuit area and the pixel cell area, respectively. A first oxide layer, a silicon nitride layer and a second oxide layer are sequentially formed on the pixel cells and the metal layers. The second oxide layer is then patterned to define a pre-determined position of a pad spacer in the pixel cell area and the peripheral circuit area. The silicon nitride layer and the first oxide layer are further defined to form a first protective layer in the peripheral circuit area and to from a pad spacer in the pixel cell area exposing the pixel cells. A second protective layer is then formed on the exposed pixel cells.

Fabrication method for a multi-layered thin film protective layer

A fabrication method for a multi-layered thin film protective layer which is applicable on a substrate comprising a peripheral circuit area and a pixel cell area is described. Metal layers and pixel cells are formed on the peripheral circuit area and the pixel cell area, respectively, wherein an insulation material is formed in the interspace between the metal layers and between the pixel cells to provide a sufficient separation. Thereafter, a first oxide layer, a silicon nitride layer and a second oxide layer are sequentially formed on the pixel cells and the metal layers. The second oxide layer is then patterned to define a pre-determined position of a pad spacer in the pixel cell area and the peripheral circuit area. The silicon nitride layer and the first oxide layer are further defined to form a first protective layer in the peripheral circuit area and to from a pad spacer in the pixel cell area exposing the pixel cells. A second protective layer is then formed on the exposed pixel cells.

A multi-layered thin film protective layer structure, which is applicable for a liquid crystal display with a substrate comprising a peripheral circuit area and a pixel cell area, is described. The pixel cell area and the peripheral circuit area comprise a plurality of pixel cells and metal layers, respectively. The multi-layered thin film protective layer also includes a protective layer in the peripheral circuit area to cover the metal layers and a plurality of pad spacers in the pixel cell area and the peripheral circuit area. The pad spacers are higher than the first protective layer. The structure also comprises a second protective layer in the pixel cell area to cover the pixel cells, wherein the second protective layer has a higher reflectivity to allow the transmission of light to reach the pixel cells and a reflection of light.

Structure of a multi-layered thin film protective layer

A method for fabricating a passivation layer and a liquid crystal display. For the fabrication method, a substrate is provided. An oxide layer, a first silicon nitride layer, a spin-on-glass (SOG) layer, and a second silicon nitride layer are sequentially formed over the substrate. The liquid crystal display has a controller, a dielectric layer, a metal layer, an oxide layer, a first silicon nitride layer, a spin-on-glass layer, and a second silicon nitride layer. The dielectric layer is positioned over the controller. A metal layer is positioned over the dielectric layer. An oxide layer is formed over the metal layer. A first silicon nitride layer is formed over the oxide layer. A spin-on-glass (SOG) layer is formed over the first silicon nitride layer. A second silicon nitride layer is formed over the SOG layer.

Method for fabricating passivation layer

A method of fabricating a preserve layer. A top metallic layer is formed over the substrate. Portions of the metallic layer and the substrate are removed to form a trench. A conformal pad oxide layer is formed over the substrate. A conformal first nitride layer is formed on the pad oxide layer. A spin-on glass layer is formed on the first nitride layer to fill the trench. An etching back step is performed to remove a portion of the spin-on glass layer. The remaining spin-on glass layer fills the trench to the surface of the first nitride layer above the top metallic layer. An oxide layer is formed over the substrate. A second nitride layer is formed on the oxide layer. A preserve layer comprising the pad oxide layer, the first nitride layer, the oxide layer, and the second nitride layer is formed.

Method of fabricating preserve layer

A method of fabricating a dummy pattern is proposed. A semiconductor substrate is divided into a dense region and a sparse region. Conducting patterns are formed on the dense region. A dielectric layer is formed over the substrate and the conducting patterns. Photoresist patterns are formed on the dielectric layer above the sparse region. The dielectric layer is etched back to form a plurality of spacers on the sidewall of the conducting patterns, and simultaneously, a plurality of dummy patterns are formed on the sparse region.

Method of manufacturing dummy pattern

A method for fabricating a passivation layer. An isolation layer is formed on a metal layer over the substrate. The isolation layer on the metal layer is removed by chemical-mechanical polishing and dry etching. The planarization of the metal layer thus is obtained. A passivation layer having a certain structure and a thickness combination of different layers is formed over the substrate. The reflection rate of the metal layer is significantly enhanced.

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China, Taiwan

Wei-Shiau Chen