Intel Corporation

Wei Ming Lim

Terrence Huat Hin Tan

Amit D Sanghani

Sreejit Chakravarty

Vui Yong Liew

Fei Su

Anubhav Sinha

Rakesh Reddy Kandula

Alvin Shing Chye Goh

Puneet Gupta

Sudheer V Badana

Kim Leong Lee

Adithya B S

Yah Chen Chew

Madhu Rao

A die-to-die repeater circuit includes a transmit circuit coupled to a die-to-die interconnect, the transmit circuit including at least one flip flop to function as a part of a linear feedback shift register (LFSR) to transmit a value across the die-to-die interconnect for design for test (DFT) to check proper operation of the die-to-die interconnect, and a receive circuit coupled to the die-to-die interconnect, the receive circuit including at least one flip flop to function as part of a multiple input shift register (MISR).

Test architecture for die to die interconnect for three dimensional integrated circuits

Methods and apparatus for predictable protocol aware testing on a memory interface are are shown. An apparatus to support a protocol aware testing on a memory interface may include a digital controller to receive a plurality of read request commands from a unit under test. The digital controller further to hold the plurality of read request commands while a hold signal has a first value, and to sequentially release individual read request commands of the plurality of read request commands while to the hold signal has a second value. The digital controller further to provide input/output (I/O) commands to an output based on a particular released read request command of the plurality of read request commands. Timing of provision of the I/O commands is deterministic based on a transition of the hold signal from the first value to the second value.

Methods and apparatus for predictable protocol aware testing on memory interface

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Bayan Lepas, Malaysia

Wei Ming Lim