Taiwan Semiconductor Manufacturing Comp. Ltd.

Wei-Min Liu

Yee-Chia Yeo

Li-Li Su

Hsueh-Chang Sung

Wei-Yang Lee

Chii-Horng Li

Chia-Pin Lin

Po-Yu Lin

Wei-Han Fan

Tzu-Hua Chiu

Kuan-Hao Cheng

LI-Li Su

Chien-I Kuo

Wei Hao Lu

Cheng-Yen Wen

A method includes flowing first precursors over a semiconductor substrate to form an epitaxial region, the epitaxial region includes a first element and a second element; converting a second precursor into first radicals and first ions; separating the first radicals from the first ions; and flowing the first radicals over the epitaxial region to remove at least some of the second element from the epitaxial region.

Semiconductor device and method of manufacture

In an embodiment, a device includes: a first nanostructure; a source/drain region adjoining a first channel region of the first nanostructure, the source/drain region including: a main layer; and a first liner layer between the main layer and the first nanostructure, a carbon concentration of the first liner layer being greater than a carbon concentration of the main layer; an inter-layer dielectric on the source/drain region; and a contact extending through the inter-layer dielectric, the contact connected to the main layer, the contact spaced apart from the first liner layer.

Methods of forming transistor source/drain regions comprising carbon liner layers

A method includes forming a stack of layers, which includes a plurality of semiconductor nano structures and a plurality of sacrificial layers. The plurality of semiconductor nano structures and the plurality of sacrificial layers are arranged alternatingly. The method further includes laterally recessing the plurality of sacrificial layers to form lateral recesses, forming inner spacers in the lateral recesses, and epitaxially growing a source/drain region from the plurality of semiconductor nano structures. The source/drain region is spaced apart from the inner spacers by air inner spacers.

Nano-structure transistors with air inner spacers and methods forming same

A device includes a first nanostructure over a semiconductor substrate; a second nanostructure over the first nanostructure; a gate structure surrounding the first nanostructure and the second nanostructure; a first epitaxial region in the semiconductor substrate adjacent the gate structure, wherein the first epitaxial region is a first doped semiconductor material; and a second epitaxial region over the first epitaxial region, wherein the second epitaxial region is adjacent the first nanostructure and the second nanostructure, wherein the second epitaxial region is a second doped semiconductor material that is different from the first doped semiconductor material. In an embodiment, the first doped semiconductor material has a smaller doping concentration than the second doped semiconductor material.

Source/drain regions of semiconductor device and method of forming the same

A method includes forming a gate structure over fins protruding from a semiconductor substrate; forming an isolation region surrounding the fins; depositing a spacer layer over the gate structure and over the fins, wherein the spacer layer fills the regions extending between pairs of adjacent fins; performing a first etch on the spacer layer, wherein after performing the first etch, first remaining portions of the spacer layer that are within inner regions extending between pairs of adjacent fins have a first thickness and second remaining portions of the spacer layer that are not within the inner regions have a second thickness less than the first thickness; and forming an epitaxial source/drain region adjacent the gate structure and extending over the fins, wherein portions of the epitaxial source/drain region within the inner regions are separated from the first remaining portions of the spacer layer.

Semiconductor device and method

A semiconductor device includes a source/drain feature over a semiconductor substrate, channel layers over the semiconductor substrate and connected to the source/drain feature, a gate portion between vertically adjacent channel layers, and an inner spacer between the source/drain feature and the gate portion and between adjacent channel layers. The semiconductor device further includes an air gap between the inner spacer and the source/drain feature.

Epitaxial structures exposed in airgaps for semiconductor devices

A device includes a first fin and a second fin extending from a substrate, the first fin including a first recess and the second fin including a second recess, an isolation region surrounding the first fin and surrounding the second fin, a gate stack over the first fin and the second fin, and a source/drain region in the first recess and in the second recess, the source/drain region adjacent the gate stack, wherein the source/drain region includes a bottom surface extending from the first fin to the second fin, wherein a first portion of the bottom surface that is below a first height above the isolation region has a first slope, and wherein a second portion of the bottom surface that is above the first height has a second slope that is greater than the first slope.

Method of manufacturing a FinFET with merged epitaxial source/drain regions

The present disclosure is directed to methods for forming source/drain (S/D) epitaxial structures with a hexagonal shape. The method includes forming a fin structure that includes a first portion and a second portion proximate to the first portion, forming a gate structure on the first portion of the fin structure, and recessing the second portion of the fin structure. The method further includes growing a S/D epitaxial structure on the recessed second portion of the fin structure, where growing the S/D epitaxial structure includes exposing the recessed second portion of the fin structure to a precursor and one or more reactant gases to form a portion of the S/D epitaxial structure. Growing the S/D epitaxial structure further includes exposing the portion of the S/D structure to an etching chemistry and exposing the portion of the S/D epitaxial structure to a hydrogen treatment to enhance growth of the S/D epitaxial structure.

Source/drain epitaxial layers for transistors

Semiconductor devices and methods of fabricating the semiconductor devices are described herein. The method includes steps for patterning fins in a multilayer stack and forming an opening in a fin as an initial step in forming a source/drain region. The opening is formed into a parasitic channel region of the fin. Once the opening has been formed, a first semiconductor material is epitaxially grown at the bottom of the opening to a level over the top of the parasitic channel region. A second semiconductor material is epitaxially grown from the top of the first semiconductor material to fill and/or overfill the opening. The second semiconductor material is differently doped from the first semiconductor material. A stack of nanostructures is formed by removing sacrificial layers of the multilayer stack, the second semiconductor material being electrically coupled to the nanostructures.

Semiconductor device having a multilayer source/drain region and methods of manufacture

A semiconductor device includes a first device region and a second device region. The first device region includes a first source/drain region extending from a substrate and a first and a second pair of spacers. The first source/drain region extends between the first pair of spacers and the second pair of spacers. The first pair of spacers and the second pair of spacers have a first height. The second device region includes a second and a third source/drain region extending from the substrate and a third and a fourth pair of spacers. The third source/drain region is separate from the second source/drain region. The second source/drain region extends between the third pair of spacers. The third source/drain region extends between the fourth pair of spacers. The third pair of spacers and the fourth pair of spacers have a second height greater than the first height.

Source/drain structures and method of forming

A device includes a fin extending from a substrate; a gate stack over and along sidewalls of the fin; a gate spacer along a sidewall of the gate stack; an epitaxial source/drain region in the fin and adjacent the gate spacer, the epitaxial source/drain region including a first epitaxial layer on the fin, the first epitaxial layer including silicon and arsenic; and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer including silicon and phosphorus, the first epitaxial layer separating the second epitaxial layer from the fin; and a contact plug on the second epitaxial layer.

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Tainan, Taiwan

Wei-Min Liu