United Microelectronics Corp.

Wei-Min Lin

Chih-Wei Yang

Wen-Tai Chiang

Wei-Tsun Shiau

Yi-Sheng Hsieh

A method for fabricating a MOS transistor is described. A gate dielectric layer, a first barrier layer, an interlayer, a work-function-dominating layer, a second barrier layer and a poly-Si layer are sequentially formed on a substrate. The interlayer is capable of adjusting the work function of the work-function-dominating layer and wetting the surface of the first barrier layer. The above layers are then patterned into a gate, and a source/drain is formed in the substrate beside the gate.

MOS transistor and fabrication thereof

A MOS transistor including a substrate, a gate dielectric layer on the substrate, a stacked gate on the gate dielectric layer, and a source/drain in the substrate beside the stacked gate is provided. In particular, the stacked gate includes, from bottom to top, a first barrier layer, an interlayer, a work-function-dominating layer, a second barrier layer and a poly-Si layer, wherein the work-function-dominating layer includes a metallic material.

Growing community of inventors

Hsinchu County, Taiwan

Wei-Min Lin