Taiwan Semiconductor Manufacturing Comp. Ltd.

Wei-kun Yeh

An-Min Chiang

Chiarn-Lung Lee

J S Shiao

A M Chiang

Shyh-Jen Guo

A method for forming a semiconductor device having a via by using a composite dielectric layer is disclosed. The method includes forming a first dielectric layer over a first conductive layer disposed on a substrate, where the first dielectric layer has a first etch rate. A second dielectric layer is then formed on the first dielectric layer, where the second dielectric layer has a second etch rate higher than the first etch rate. The second dielectric layer is isotropically removed by masking and etching to form a rounded contoured recess in the second dielectric layer using the first dielectric layer as an etch stop layer. The first dielectric layer is anisotropically removed by masking and etching to form the via in the first dielectric layer, where the bottom of the rounded contoured recess is aligned to the via.

Via structure using a composite dielectric layer

A method for forming patterned conductor metallization layers adjoining patterned barrier metallization layers upon semiconductor substrates. A semiconductor substrate is provided which has formed upon its surface a patterned second masking layer upon a blanket first masking layer. The patterned second masking layer is formed from a photoresist material and the blanket first masking layer is formed from a silicon oxide material, a silicon nitride material or a silicon oxynitride material. Beneath the blanket first masking layer resides a blanket multi-layer metallization stack which includes a blanket conductor metallization layer adjoining a blanket barrier metallization layer. The blanket first masking layer and the upper lying blanket metallization layer of the blanket conductor metallization layer and the blanket barrier metallization layer are successively patterned through a Reactive Ion Etch (RIE) process using as the etch mask the patterned second masking layer. The patterned second masking layer is then removed. The remaining lower lying metallization layer is then patterned through a Reactive Ion Etch (RIE) process using a patterned first masking layer and the patterned upper metallization layer as the etch mask.

Method of multi-step reactive ion etch for patterning adjoining

A new method of forming a high quality silicon oxide under a gate electrode for an integrated circuit is described. A gate silicon oxide layer is formed for the gate electrode. A blockout mask is provided for all areas of the integrated circuit not requiring an ion implant. The ion implant is implanted through the gate silicon oxide layer into those areas not covered by the blockout mask. The blockout mask is removed. The gate silicon oxide layer is cleaned to improve the electrical breakdown and charge breakdown characteristics to the state they were before the mask and ion implanting steps by a) treating the gate silicon oxide layer with ammonia and peroxide fluid in the concentration NH.sub.4 OH:H.sub.2 O.sub.2 :H.sub.2 O=(0.4-1):1:5.5 for between about 3 to 7 minutes at a temperature of between about 60.degree. to 80.degree. C. and b) subjecting the gate silicon oxide layer to an atmosphere of C.sub.2 H.sub.2 Cl.sub.2 and excess oxygen at a temperature of between about 775.degree. to 875.degree. C. for a time of between about 5 to 25 minutes. A polysilicon layer is deposited over the gate silicon oxide layer and patterned to form the gate electrode.

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Hsinchu, Taiwan

Wei-kun Yeh