Taiwan Semiconductor Manufacturing Comp. Ltd.

Chang Chun Plastics Co., Ltd.

International Currency Technologies Corporation

Wei-Jung Lin

Ming-Hsing Tsai

Chih-Wei Chang

Hong-Mao Lee

Chun-Hsien Huang

Chun-I Tsai

Cheng-Tung Lin

Chia-Han Lai

Ken-Yu Chang

Chi-Yuan Chen

Ya-Yi Cheng

Chih-wei Chang

Pin-Wen Chen

Teng-Chun Tsai

Mei-Yun Wang

Li-Ting Wang

Sheng-Hsuan Lin

Yan-Ming Tsai

Huang-Yi Huang

Hung-Chang Hsu

Mei-Hui Fu

I-Li Chen

Yu-Kai Chen

Wei-Yip Loh

Yu Shih Wang

Yu-Wen Cheng

Hsien-Lung Yang

Yu-Shiuan Wang

Huicheng Chang

Chii-Ming M Wu

Yu-Hung Lin

Chun-Wen Nieh

Shian Wei Mao

Chang-Ting Chung

Chi-Hsuan Ni

Kuo-Yi Chao

Chao-Hsun Wang

Chen-Yuan Kao

Po-Yu Huang

Hung-Hsu Chen

Min-Hsiu Hung

Rueijer Lin

Shih-Che Lin

Feng-Yu Chang

Kai-Chieh Yang

Yuan-Chen Hsu

Yu-Chen Ko

Yu-Ting Wen

Shau-Lin Shue

Wei-Cheng Lin

You-Hua Chou

Chen-Ming Lee

Chia-Lin Hsu

Li-Wei Chu

Hon-Lin Huang

Shih-Chi Lin

Fang-Cheng Chen

Yi-Hsiang Chao

Yu-Hsiang Liao

Wen-Chi Tsai

Peng-Hao Hsu

Chih-Hao Wang

Ching-Wei Tsai

Carlos H Diaz

Shih-Chang Chen

Shing-Chyang Pan

Hui-Cheng Chang

Ching-Yi Chen

Bing-Hung Chen

Wen-Chang Chen

Huan-Tsung Huang

Yu-Shih Wang

Hsueh-Hung Fu

Tsung-Hsun Huang

Kevin Lee

Shu-Lan Chang

Pei-Wen Wu

Chih-Ching Liao

Chin-Piao Chang

Chih-Hsu Tsai

Shih-Wei Yeh

Pei Shan Chang

Yu Shih Shih Wang

The present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In some embodiments, a structure includes a first dielectric layer over a substrate, a first conductive feature through the first dielectric layer, the first conductive feature comprising a first metal, a second dielectric layer over the first dielectric layer, and a second conductive feature through the second dielectric layer having a lower convex surface extending into the first conductive feature, wherein the lower convex surface of the second conductive feature has a tip end extending laterally under a bottom boundary of the second dielectric layer.

Conductive feature formation and structure using bottom-up filling deposition

A method includes forming a dielectric layer over a source/drain region. An opening is formed in the dielectric layer. The opening exposes a portion of the source/drain region. A conductive liner is formed on sidewalls and a bottom of the opening. A surface modification process is performed on an exposed surface of the conductive liner. The surface modification process forms a surface coating layer over the conductive liner. The surface coating layer is removed to expose the conductive liner. The conductive liner is removed from the sidewalls of the opening. The opening is filled with a conductive material in a bottom-up manner. The conductive material is in physical contact with a remaining portion of the conductive liner and the dielectric layer.

Contact features of semiconductor device and method of forming same

A method includes depositing an inter-layer dielectric (ILD) over a source/drain region; forming a contact opening through the ILD, wherein the contact opening exposes the source/drain region; forming a metal-semiconductor alloy region on the source/drain region; depositing a first layer of a conductive material on the metal-semiconductor alloy region; depositing an isolation material along sidewalls of the contact opening and over the first layer of the conductive material; etching the isolation material to expose the first layer of the conductive material, wherein the isolation material extends along sidewalls of the contact opening after etching the isolation material; and depositing a second layer of the conductive material on the first layer of the conductive material.

Transistor source/drain contacts and methods of forming the same

Embodiments disclosed herein relate generally to forming an effective metal diffusion barrier in sidewalls of epitaxy source/drain regions. In an embodiment, a structure includes an active area having a source/drain region on a substrate, a dielectric layer over the active area and having a sidewall aligned with the sidewall of the source/drain region, and a conductive feature along the sidewall of the dielectric layer to the source/drain region. The source/drain region has a sidewall and a lateral surface extending laterally from the sidewall of the source/drain region, and the source/drain region further includes a nitrided region extending laterally from the sidewall of the source/drain region into the source/drain region. The conductive feature includes a silicide region along the lateral surface of the source/drain region and along at least a portion of the sidewall of the source/drain region.

Contact with a silicide region

Methods of forming a semiconductor device structure are described. In some embodiments, the method includes forming a contact opening in an interlayer dielectric (ILD) layer disposed over an epitaxy source/drain region and forming a metal layer in the contact opening. The metal layer includes top portions, side portions, and a bottom portion, and a space is defined between the top portions of the metal layer. The method further includes performing a gradient metal removal process on the metal layer to enlarge the space, forming a sacrificial layer in the contact opening, recessing the sacrificial layer in the contact opening to expose a portion of the sidewall portions, removing the top portions and the exposed portion of the sidewall portions, removing the sacrificial layer, and forming a bulk metal layer on the bottom portion of the metal layer.

Methods of forming semiconductor device structures

A method includes forming a first metallic feature, forming a dielectric layer over the first metallic feature, etching the dielectric layer to form an opening, with a top surface of the first metallic feature being exposed through the opening, and performing a first treatment on the top surface of the first metallic feature. The first treatment is performed through the opening, and the first treatment is performed using a first process gas. After the first treatment, a second treatment is performed through the opening, and the second treatment is performed using a second process gas different from the first process gas. A second metallic feature is deposited in the opening.

Phase control in contact formation

Vias, along with methods for fabricating vias, are disclosed that exhibit reduced capacitance and resistance. An exemplary interconnect structure includes a first source/drain contact and a second source/drain contact disposed in a dielectric layer. The first source/drain contact physically contacts a first source/drain feature and the second source/drain contact physically contacts a second source/drain feature. A first via having a first via layer configuration, a second via having a second via layer configuration, and a third via having a third via layer configuration are disposed in the dielectric layer. The first via and the second via extend into and physically contact the first source/drain contact and the second source/drain contact, respectively. A first thickness of the first via and a second thickness of the second via are the same. The third via physically contacts a gate structure, which is disposed between the first source/drain contact and the second source/drain contact.

Different via configurations for different via interface requirements

A method includes forming a dielectric layer over an epitaxial source/drain region. An opening is formed in the dielectric layer. The opening exposes a portion of the epitaxial source/drain region. A barrier layer is formed on a sidewall and a bottom of the opening. An oxidation process is performing on the sidewall and the bottom of the opening. The oxidation process transforms a portion of the barrier layer into an oxidized barrier layer and transforms a portion of the dielectric layer adjacent to the oxidized barrier layer into a liner layer. The oxidized barrier layer is removed. The opening is filled with a conductive material in a bottom-up manner. The conductive material is in physical contact with the liner layer.

A method of fabricating a contact structure includes the following steps. An opening is formed in a dielectric layer. A conductive material layer is formed within the opening and on the dielectric layer, wherein the conductive material layer includes a bottom section having a first thickness and a top section having a second thickness, the second thickness is greater than the first thickness. A first treatment is performed on the conductive material layer to form a first oxide layer on the bottom section and on the top section of the conductive material layer. A second treatment is performed to remove at least portions of the first oxide layer and at least portions of the conductive material layer, wherein after performing the second treatment, the bottom section and the top section of the conductive material layer have substantially equal thickness.

Method of fabricating contact structure

A semiconductor device is disclosed. The device includes a source/drain feature formed over a substrate. A dielectric layer formed over the source/drain feature. A contact trench formed through the dielectric layer to expose the source/drain feature. A titanium nitride (TiN) layer deposited in the contact trench and a cobalt layer deposited over the TiN layer in the contact trench.

Method of forming contact metal

Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back by a wet etching process. After etching back the portion of the barrier layer, an underlying dielectric welding layer is exposed. A conductive material is formed along the barrier layer.

Contact conductive feature formation and structure

Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back. After etching back the portion of the barrier layer, an upper portion of the barrier layer along the sidewall is smoothed. A conductive material is formed along the barrier layer and over the smoothed upper portion of the barrier layer.

Conductive feature formation and structure

Methods of forming contacts for source/drain regions and a contact plug for a gate stack of a finFET device are disclosed herein. Methods include etching a contact opening through a dielectric layer to expose surfaces of a first source/drain contact and repairing silicon oxide structures along sidewall surfaces of the contact opening and along planar surfaces of the dielectric layer to prevent selective loss defects from occurring during a subsequent selective deposition of conductive fill materials and during subsequent etching of other contact openings. The methods further include performing a selective bottom-up deposition of conductive fill material to form a second source/drain contact. According to some of the methods, once the second source/drain contact has been formed, the contact plug may be formed over the gate stack.

Semiconductor device

Growing community of inventors

Hsinchu, Taiwan

Wei-Jung Lin